Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
05/2005
05/12/2005US20050099878 Parallel electrode memory
05/12/2005US20050099876 Semiconductor integrated circuit and data processing system
05/12/2005US20050099874 Semiconductor integrated circuit device
05/12/2005US20050099871 Semiconductor integrated circuit
05/12/2005US20050099870 Non-volatile semiconductor memory with large erase blocks storing cycle counts
05/12/2005US20050099868 Refresh for dynamic cells with weak retention
05/12/2005US20050099866 Method and circuit for determining sense amplifier sensitivity
05/12/2005US20050099865 Magnetoresistive element, magnetic memory cell, and magnetic memory device
05/12/2005US20050099864 Metal programmable self-timed memories
05/12/2005US20050099859 Floating-gate semiconductor structures
05/12/2005US20050099858 Encoding circuit for semiconductor device and redundancy control circuit using the same
05/12/2005US20050099855 System and method for determining the logic state of a memory cell in a magnetic tunnel junction memory device
05/12/2005US20050099850 Memory device
05/12/2005US20050099848 Non-volatile semiconductor memory device and electric device with the same
05/12/2005US20050099847 Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems
05/12/2005US20050099845 Erase block data splitting
05/12/2005US20050099844 Magnetic non-volatile memory coil layout architecture and process integration scheme
05/12/2005US20050099841 Networked processor for a pipeline architecture
05/12/2005US20050099840 Semiconductor integrated circuit
05/12/2005US20050099838 Nonvolatile ferroelectric memory device having power control function
05/12/2005US20050099837 Semiconductor memory device for controlling write recovery time
05/12/2005US20050099836 Isolation device over field in a memory device
05/12/2005US20050099834 Stacked memory, memory module and memory system
05/12/2005US20050099756 Semiconductor device
05/12/2005US20050099724 Magnetic device and magnetic memory
05/12/2005US20050099445 Printing cartridge with capacitive sensor identification
05/12/2005US20050099375 Display memory, driver circuit, display, and cellular information apparatus
05/12/2005US20050098881 Memory module and method for operating a memory module
05/12/2005US20050098823 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
05/12/2005US20050098810 Semiconductor memory devices and methods of fabricating semiconductor memory device
05/12/2005US20050098809 Antiferromagnetic stabilized storage layers in GMRAM storage devices
05/12/2005US20050098807 Bias-adjusted giant magnetoresistive (GMR) devices for magnetic random access memory (MRAM) applications
05/12/2005US20050098800 Nonvolatile memory cell comprising a reduced height vertical diode
05/12/2005US20050098428 Silver selenide film stoichiometry and morphology control in sputter deposition
05/12/2005US20050097725 Method for fabricating giant magnetoresistive (GMR) devices
05/12/2005DE10357777B3 Verfahren zum Betrieb eines Speicherzellenfeldes A method of operating a memory cell array
05/12/2005DE10333522B4 Speicheranordnung zur Verarbeitung von Daten und Verfahren Memory means for processing data and methods
05/11/2005EP1530219A2 Semiconductor memory with synchronous and asynchronous mode selection during power-down
05/11/2005EP1530218A2 Semiconductor integrated circuit having temperature detector
05/11/2005EP1530217A2 Semiconductor integrated circuit having temperature detector
05/11/2005EP1529291A2 Seu resistant sram using feedback mosfet
05/11/2005EP1529290A2 Memories and memory circuits
05/11/2005CN2699433Y Magneto-resistive type storing unit structure and magneto-resistive type random access memory circuit
05/11/2005CN1615524A Method and apparatus for standby power reduction in semiconductor devices
05/11/2005CN1614784A 集成半导体内存 Integrated semiconductor memory
05/11/2005CN1614781A 半导体集成电路 The semiconductor integrated circuit
05/11/2005CN1614716A 半导体存储器 Semiconductor memory
05/11/2005CN1614715A Strong dielectric memory device and electronic device
05/11/2005CN1614714A Double-magnetic tunnel junction with high magnetic resistance effect and preparing method thereof
05/11/2005CN1614713A Stacked memory, memory module and memory system
05/11/2005CN1201401C Semiconductor device
05/11/2005CN1201395C Semiconductor integrated circuit and its design method
05/11/2005CN1201334C Method for reducing power consumption in DRAM
05/11/2005CN1201333C Integrated storage with storage unit having magnetic-resistance storage effect and its operation method
05/11/2005CN1201332C Semiconductor memory and method for replacing faitured unit therein
05/11/2005CN1201331C Arrangement for controlling voltage generators in multi-voltage generator chips
05/11/2005CN1201264C Power supply circuit building in integrated circuit
05/10/2005US6891775 Asynchronous pseudo SRAM
05/10/2005US6891774 Delay line and output clock generator using same
05/10/2005US6891772 High speed DRAM architecture with uniform access latency
05/10/2005US6891770 Fully hidden refresh dynamic random access memory
05/10/2005US6891769 Flash/dynamic random access memory field programmable gate array
05/10/2005US6891768 Power-saving reading of magnetic memory devices
05/10/2005US6891767 Semiconductor memory device and method for pre-charging the same
05/10/2005US6891763 Input buffer with differential amplifier
05/10/2005US6891759 Semiconductor memory having electrically erasable and programmable semiconductor memory cells
05/10/2005US6891750 Structure and method for transverse field enhancement
05/10/2005US6891748 MRAM having memory cell array in which cross-point memory cells are arranged by hierarchical bit line scheme and data read method thereof
05/10/2005US6891747 Phase change memory cell and manufacturing method thereof using minitrenches
05/10/2005US6891746 Magneto-resistive device having soft reference layer
05/10/2005US6891745 Design concept for SRAM read margin
05/10/2005US6891743 Semiconductor memory device having a capacitive plate to reduce soft errors
05/10/2005US6891742 Semiconductor memory device
05/10/2005US6891741 Ferroelectric memory device
05/10/2005US6891416 Timing generation circuit and method for timing generation
05/10/2005US6891404 Auto-adjustment of self-refresh frequency
05/10/2005US6891393 Synchronous semiconductor device, and inspection system and method for the same
05/10/2005US6891241 Single transistor type magnetic random access memory device and method of operating and manufacturing the same
05/10/2005US6891212 Magnetic memory device having soft reference layer
05/10/2005US6891205 Stability in thyristor-based memory device
05/10/2005US6891185 Electronic device with aperture and wide lens for small emission spot size
05/10/2005US6890875 Tunable devices incorporating BiCu3Ti3FeO12
05/10/2005US6890767 Method to reduce switch threshold of soft magnetic films
05/06/2005WO2005041303A1 Resistance change element, manufacturing method thereof, memory including the element, and drive method of the memory
05/06/2005WO2005041270A2 Mram array with segmented word and bit lines
05/06/2005WO2005041206A2 Method, system and circuit for programming a non-volatile memory array
05/06/2005WO2005041203A1 Semiconductor storage device
05/06/2005WO2005041202A1 Random access memory having self-adjusting off-chip driver
05/06/2005WO2005041201A1 Semiconductor storage device and method for refreshing the same
05/06/2005WO2005041200A1 Auto-refresh multiple row activation
05/06/2005WO2005041199A1 Method and circuit configuration for multiple charge recycling during refresh operations in a dram device
05/06/2005WO2005041198A1 Selective bank refresh
05/06/2005WO2005041195A1 Reference current distribution in mram devices
05/06/2005WO2005041194A1 Random access memory with data strobe locking circuit
05/06/2005WO2005041108A2 A method circuit and system for read error detection in a non-volatile memory array
05/06/2005WO2005041107A2 A method circuit and system for determining a reference voltage
05/06/2005WO2005006337A3 Variable gate bias for a reference transistor in a non-volatile memory
05/06/2005WO2004093085A3 Method and system for providing a magnetic memory having a wrapped write line
05/06/2005WO2004066093A3 Distributed memory computing environment and implantation thereof
05/06/2005WO2004049345A3 Magnetic memory architecture with shared current line
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