Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
05/2005
05/25/2005CN1619697A Semiconductor memory having sense amplifier architecture
05/25/2005CN1203560C Magnetic memory element, magnetic memory and method for mfg magnetic memory
05/25/2005CN1203550C Memory, recording device, reading-out device, recording method and reading-out method
05/25/2005CN1203545C Semiconductor storage apparatus
05/25/2005CN1203487C Semiconductor memory
05/24/2005US6898683 Clock synchronized dynamic memory and clock synchronized integrated circuit
05/24/2005US6898663 Programmable refresh scheduler for embedded DRAMs
05/24/2005US6898145 Distributed, highly configurable modular predecoding
05/24/2005US6898144 Actively driven VREF for input buffer noise immunity
05/24/2005US6898142 Semiconductor memory, method for controlling refreshment of it, and method for setting memory cell array specific area for realizing the control method
05/24/2005US6898141 Dynamic semiconductor memory device and method of controlling refresh thereof
05/24/2005US6898140 Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors
05/24/2005US6898139 Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation
05/24/2005US6898138 Method of reducing variable retention characteristics in DRAM cells
05/24/2005US6898137 Semiconductor memory device with high-speed sense amplifier
05/24/2005US6898136 Semiconductor memory device, capable of reducing power consumption
05/24/2005US6898134 Systems and methods for sensing a memory element
05/24/2005US6898132 System and method for writing to a magnetic shift register
05/24/2005US6898130 Semiconductor memory device and defect remedying method thereof
05/24/2005US6898128 Programming of a memory with discrete charge storage elements
05/24/2005US6898126 Method of programming a flash memory through boosting a voltage level of a source line
05/24/2005US6898125 Semiconductor device and method for driving the same
05/24/2005US6898124 Efficient and accurate sensing circuit and technique for low voltage flash memory devices
05/24/2005US6898121 Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND
05/24/2005US6898118 Clock synchronized non-volatile memory device
05/24/2005US6898117 Multi-bit-per-cell flash EEPROM memory with refresh
05/24/2005US6898115 Magnetoresistive element, and magnetic memory using the same
05/24/2005US6898114 Memory device capable of stable data writing
05/24/2005US6898113 Magnetic memory device with reference cell for data reading
05/24/2005US6898112 Synthetic antiferromagnetic structure for magnetoelectronic devices
05/24/2005US6898111 SRAM device
05/24/2005US6898109 Semiconductor memory device in which bit lines connected to dynamic memory cells extend left and right of sense amplifier column
05/24/2005US6898108 Semiconductor storage device and method for driving the same
05/24/2005US6898107 Nonvolatile FeRAM control device
05/24/2005US6898106 Using FeRam/MRAM cells having a high degree of flexibility and compact construction and method of operating the memory device
05/24/2005US6898105 Ferroelectric non-volatile memory device having integral capacitor and gate electrode, and driving method of a ferroelectric non-volatile memory device
05/24/2005US6898104 Semiconductor device having semiconductor memory with sense amplifier
05/24/2005US6898103 Memory cell with fuse element
05/24/2005US6898102 Digitline architecture for dynamic memory
05/24/2005US6898100 Semiconductor memory device used for cache memory
05/24/2005US6897708 Semiconductor booster circuit requiring no transistor elements having a breakdown voltage of substantially twice the power supply voltage
05/24/2005US6897705 Semiconductor device using current mirror circuit
05/24/2005US6897684 Input buffer circuit and semiconductor memory device
05/24/2005US6897522 Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
05/24/2005US6897499 Semiconductor integrated circuit device including MISFETs each with a gate electrode extended over a boundary region between an active region and an element isolation trench
05/24/2005US6897101 Method for writing to the magnetoresistive memory cells of an integrated magnetoresistive semiconductor memory
05/24/2005US6895658 Includes a free layer formed on a lower gap layer, a tunnel barrier layer formed on the free layer, and a pinned layer formed on the tunnel barrier layer
05/19/2005WO2005045935A2 Sidewall formation for high density polymer memory element array
05/19/2005WO2005045846A1 Semiconductor storage device and burst operation method thereof
05/19/2005WO2005045845A1 Refresh for dynamic cells with weak retention
05/19/2005WO2005045821A1 Dielectric memory element
05/19/2005WO2005045679A1 Controller of synchronous memory and electronic device
05/19/2005WO2005045373A1 Memory device, memory control method and display device
05/19/2005US20050108468 Memory device with programmable receivers to improve performance
05/19/2005US20050108460 Partial bank DRAM refresh
05/19/2005US20050108459 Integrated memory circuit
05/19/2005US20050106818 [memory device and fabrication method thereof]
05/19/2005US20050106810 Stress assisted current driven switching for magnetic memory applications
05/19/2005US20050106760 Method for increasing ferroelectric characteristics of polymer memory cells
05/19/2005US20050105381 Memory system and approach
05/19/2005US20050105380 Semiconductor memory device and control method thereof
05/19/2005US20050105379 High-speed synchronus memory device
05/19/2005US20050105378 Power supply circuit for delay locked loop and its method
05/19/2005US20050105377 Memory device with improved output operation margin
05/19/2005US20050105376 Data output control circuit
05/19/2005US20050105375 Magnetic random access memory
05/19/2005US20050105373 Nonvolatile semiconductor memory device
05/19/2005US20050105372 Semiconductor memory
05/19/2005US20050105371 Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement
05/19/2005US20050105369 Device, system and method for reducing power in a memory device during standby modes
05/19/2005US20050105368 Energy storing memory circuit
05/19/2005US20050105367 Internal voltage generator with temperature control
05/19/2005US20050105363 Semiconductor memory device having column address path therein for reducing power consumption
05/19/2005US20050105362 Semiconductor memory device for performing refresh operation
05/19/2005US20050105358 Sense amplifier systems and a matrix-addressable memory device provided therewith
05/19/2005US20050105357 Method and circuit configuration for refreshing data in a semiconductor memory
05/19/2005US20050105355 Method for homogeneously magnetizing an exchange-coupled layer system of a digital magnetic memory location device
05/19/2005US20050105354 Bitline precharge timing scheme to improve signal margin
05/19/2005US20050105353 Method for operating a memory cell array
05/19/2005US20050105352 Temperature compensated self-refresh (TCSR) circuit having a temperature sensor limiter
05/19/2005US20050105347 Magnetic storage unit using ferromagnetic tunnel junction element
05/19/2005US20050105344 Memory device and method for writing data in memory cell with boosted bitline voltage
05/19/2005US20050105342 Floating-body dram with two-phase write
05/19/2005US20050105341 NROM flash memory with self-aligned structural charge separation
05/19/2005US20050105339 Nonvolatile memory
05/19/2005US20050105338 Negatively biasing deselected memory cells
05/19/2005US20050105337 Method, system and circuit for programming a non-volatile memory array
05/19/2005US20050105336 Nonvolatile semiconductor memory
05/19/2005US20050105332 Memory device and fabrication method thereof
05/19/2005US20050105331 Memory system having flash memory where a one-time programmable block is included
05/19/2005US20050105330 Semiconductor memory device and manufacturing method thereof
05/19/2005US20050105329 Serial transistor-cell array architecture
05/19/2005US20050105328 Perpendicular MRAM with high magnetic transition and low programming current
05/19/2005US20050105327 Serial transistor-cell array architecture
05/19/2005US20050105326 Semiconductor device
05/19/2005US20050105325 Magnetic cell and magnetic memory
05/19/2005US20050105324 Domino comparator capable for use in a memory array
05/19/2005US20050105323 System and method for reducing leakage in memory cells using wordline control
05/19/2005US20050105322 Semiconductor memory
05/19/2005US20050105321 Nonvolatile ferroelectric memory device
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