Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
05/2005
05/19/2005US20050105320 Method and apparatus of determining a recording location on a high-density recording medium
05/19/2005US20050105318 Memory module, memory chip, and memory system
05/19/2005US20050105317 Data processor including an authentication function for judging access right
05/19/2005US20050105316 Multi chip package type memory system and a replacement method of replacing a defect therein
05/19/2005US20050105294 Data output driver that controls slew rate of output signal according to bit organization
05/19/2005US20050104923 Printhead capping arrangement
05/19/2005US20050104922 Inkjet printhead with integral nozzle plate
05/19/2005US20050104640 Apparatus and method for duty cycle correction
05/19/2005US20050104639 Modular dll architecture for generating multiple timings
05/19/2005US20050104638 Clock control method and circuit
05/19/2005US20050104627 Semiconductor device having sense amplifier driver with capacitor affected by off current
05/19/2005US20050104620 Semiconductor device
05/19/2005US20050104566 Back-bias voltage generator with temperature control
05/19/2005US20050104232 [memory device and fabrication method thereof]
05/19/2005US20050104193 Semiconductor device with magnetically permeable heat sink
05/19/2005US20050104175 Semiconductor device
05/19/2005US20050104146 Thin film device and a method of providing thermal assistance therein
05/19/2005US20050104133 Semiconductor integrated circuit device
05/19/2005US20050104119 Floating-gate semiconductor structures
05/19/2005US20050104118 Floating-gate semiconductor structures
05/19/2005US20050104105 Differential negative resistance memory
05/19/2005US20050104104 High temperature memory device
05/19/2005US20050104102 Magnetic storage device comprising memory cells including magneto-resistive elements
05/19/2005US20050104101 Spin-current switched magnetic memory element suitable for circuit integration and method of fabricating the memory element
05/19/2005US20050103980 High temperature imaging device
05/19/2005DE19842852B4 Integrierter Speicher Built-in Memory
05/19/2005DE10358026B3 Read-out signal enhancement method for memory with passive memory elements using selective inversion of logic level of information bits during information write-in
05/19/2005DE102004043855A1 Verfahren zur Herstellung einer Magnet-Tunnel-Junction-Vorrichtung A method of manufacturing a magnetic tunnel junction device
05/19/2005DE102004033113A1 Magnetspeichervorrichtung A magnetic memory device
05/19/2005DE102004030591A1 Magnetischer Speicher, der Veränderungen zwischen einem ersten und einem zweiten Widerstandszustand einer Speicherzelle erfasst Detected magnetic memory that changes between a first and a second resistance state of a memory cell
05/19/2005DE102004024634A1 Baustein und Speichersystem mit Datenpuffer sowie zugehöriges Steuerverfahren And block storage system with data buffer and associated control method
05/18/2005EP1531481A2 Magnetic tunneling junction cell having free magnetic layer with low magnetic moment and magnetic random access memory having the same
05/18/2005EP1530803A2 Nrom memory cell, memory array, related devices an methods
05/18/2005EP1446805B1 Electrodes, method and apparatus for memory structure
05/18/2005CN1618169A Active termination circuit and method for controlling the impedance of external integrated circuit terminals
05/18/2005CN1618129A Negative differential resistance field effect transistor (NDR-FET) and circuits using the same
05/18/2005CN1618106A Memory cell utilizing negative differential resistance field-effect transistors
05/18/2005CN1618105A Half density ROM embedded DRAM
05/18/2005CN1618104A Sequential nibble burst ordering for data
05/18/2005CN1618091A Compact display assembly
05/18/2005CN1617346A Semiconductor memory device and manufacturing method thereof
05/18/2005CN1617336A 半导体集成电路装置 The semiconductor integrated circuit device
05/18/2005CN1617260A Encoding circuit for semiconductor device and redundancy control circuit using the same
05/18/2005CN1617259A 数字信号处理器 Digital Signal Processor
05/18/2005CN1617258A Magnetic tunneling junction cell and magnetic random access memory
05/18/2005CN1617257A Magnetic random access storage
05/18/2005CN1617078A Phase controlled high speed interfaces
05/18/2005CN1202530C Static semiconductor memory device operating at high speed under lower power supply voltage
05/17/2005US6895543 Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
05/17/2005US6895522 Method and apparatus for compensating duty cycle distortion in a data output signal from a memory device by delaying and distorting a reference clock
05/17/2005US6895474 Synchronous DRAM with selectable internal prefetch size
05/17/2005US6894947 Semiconductor integrated circuit for a liquid crystal display driver system
05/17/2005US6894946 Methods of operating memory systems in which an active termination value for a memory device is determined at a low clock frequency and commands are applied to the memory device at a higher clock frequency
05/17/2005US6894945 Clock synchronous semiconductor memory device
05/17/2005US6894943 Semiconductor memory device which reduces the consumption current at the time of operation
05/17/2005US6894942 Refresh control circuit and method for semiconductor memory device
05/17/2005US6894940 Semiconductor memory device having a sub-amplifier configuration
05/17/2005US6894938 System and method of calibrating a read circuit in a magnetic memory
05/17/2005US6894937 Accelerated life test of MRAM cells
05/17/2005US6894934 Non-volatile memory cell sensing circuit, particularly for low power supply voltages and high capacitive load values
05/17/2005US6894933 Buffer amplifier architecture for semiconductor memory circuits
05/17/2005US6894930 Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND
05/17/2005US6894926 Multi-state memory
05/17/2005US6894925 Flash memory cell programming method and system
05/17/2005US6894923 Magnetic memory device
05/17/2005US6894922 Memory device capable of performing high speed reading while realizing redundancy replacement
05/17/2005US6894920 Magnetic random access memory (MRAM) for spontaneous hall effect and method of writing and reading data using the MRAM
05/17/2005US6894919 Magnetic random access memory
05/17/2005US6894918 Shared volatile and non-volatile memory
05/17/2005US6894917 DRAM refresh scheme with flexible frequency for active and standby mode
05/17/2005US6894916 Memory array employing single three-terminal non-volatile storage elements
05/17/2005US6894915 Method to prevent bit line capacitive coupling
05/17/2005US6894912 Semiconductor memory
05/17/2005US6894694 Producing automatic “painting” effects in images
05/17/2005US6894549 Ferroelectric non-volatile logic elements
05/17/2005US6894547 Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit
05/17/2005US6894535 Method and apparatus for ensuring signal integrity in a latch array
05/17/2005US6894344 Semiconductor integrated circuit having two switch transistors formed between two diffusion-layer lines
05/17/2005US6894339 Flash memory with trench select gate and fabrication process
05/17/2005US6894330 Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor
05/17/2005US6894304 Apparatus and method for dual cell common electrode PCRAM memory device
05/17/2005US6893741 Ruthenium and iron alloy; doubling exchange coupling; hexa-gonal close packed crystalline structure compatible with cobalt alloy ferromagnetic layers
05/12/2005WO2005043548A1 Programming method based on the behaviour of non-volatile memory cenlls
05/12/2005WO2005043547A1 Mram and methods for reading the mram
05/12/2005WO2005043546A1 Magnetoresistive memory cell and method for producing the same
05/12/2005WO2005043545A1 Nano-contacted magnetic memory device
05/12/2005WO2005043544A1 Memory assembly and method for operating the same
05/12/2005WO2005043543A1 Semiconductor integrated memory
05/12/2005WO2005043541A2 Method and system for providing a programmable current source for a magnetic memory
05/12/2005WO2005001839A3 High performance gain cell architecture
05/12/2005WO2005001490A3 Thermally operated switch control memory cell
05/12/2005US20050102581 Active compensation for operating point drift in MRAM write operation
05/12/2005US20050102577 Method and circuitry for debugging/updating ROM
05/12/2005US20050102576 Multi-sample read circuit having test mode of operation
05/12/2005US20050102466 Non-volatile semiconductor memory with large erase blocks storing cycle counts
05/12/2005US20050101088 Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells
05/12/2005US20050101086 Conductive memory stack with non-uniform width
05/12/2005US20050101079 Bit end design for pseudo spin valve (PSV) devices
05/12/2005US20050099880 Duty cycle distortion compensation for the data output of a memory device
05/12/2005US20050099879 Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell
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