Patents
Patents for G11C 11 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (76,008)
05/2005
05/03/2005US6888745 Nonvolatile memory device
05/03/2005US6888744 Selection device for a semiconductor memory device
05/03/2005US6888743 MRAM architecture
05/03/2005US6888742 Off-axis pinned layer magnetic element utilizing spin transfer and an MRAM device using the magnetic element
05/03/2005US6888741 Secure and static 4T SRAM cells in EDRAM technology
05/03/2005US6888740 Two-transistor SRAM cells
05/03/2005US6888738 Methods of writing junction-isolated depletion mode ferroelectric memory devices
05/03/2005US6888737 Ferroelectric memory and method of reading the same
05/03/2005US6888736 Ferroelectric transistor for storing two data bits
05/03/2005US6888735 Ferroelectric-type nonvolatile semiconductor memory
05/03/2005US6888734 High speed data bus
05/03/2005US6888185 Junction-isolated depletion mode ferroelectric memory devices
05/03/2005US6888184 Shielded magnetic ram cells
05/03/2005US6886751 Compact display assembly
04/2005
04/28/2005WO2005038864A2 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
04/28/2005WO2005038812A1 Semiconductor storage device and method for writing data into semiconductor storage device
04/28/2005WO2005038811A1 Memory arrangement comprising a plurality of ram modules
04/28/2005WO2005038809A1 Synchronous ram memory circuit
04/28/2005WO2005010869A3 Method of archiving data
04/28/2005WO2005010638A3 Method and system for optimizing reliability and performance of programming data in non-volatile memory devices
04/28/2005WO2005008674A3 Semiconductor memory having a short effective word-line cycle time and data readout method for said semi-conductor memory
04/28/2005WO2004082143A3 Multi-frequency synchronizing clock signal generator
04/28/2005US20050091477 Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme
04/28/2005US20050091440 Memory system and memory module
04/28/2005US20050090058 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
04/28/2005US20050090023 Method of forming ferroelectric memory cell
04/28/2005US20050088906 Semiconductor memory device having different synchronizing timings depending on the value of CAS latency
04/28/2005US20050088905 Curvature anisotropy in magnetic bits for a magnetic random access memory
04/28/2005US20050088903 Semiconductor memory device of hierarchy word type and sub word driver circuit
04/28/2005US20050088902 Method and apparatus for supplementary command bus
04/28/2005US20050088895 DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM
04/28/2005US20050088894 Auto-refresh multiple row activation
04/28/2005US20050088893 Noise resistant small signal sensing circuit for a memory device
04/28/2005US20050088892 Noise resistant small signal sensing circuit for a memory device
04/28/2005US20050088891 [device and method for breaking leakage current path of memory device and structure of memory device]
04/28/2005US20050088886 Semiconductor integrated circuit
04/28/2005US20050088884 Hybrid semiconductor - magnetic spin based memory with low transmission barrier
04/28/2005US20050088882 Semiconductor device having input/output sense amplifier for multiple sampling
04/28/2005US20050088881 Semiconductor memory device driven with low voltage
04/28/2005US20050088876 Bridge-type magnetic random access memory (MRAM) latch
04/28/2005US20050088875 Sensor compensation for environmental variations for magnetic random access memory
04/28/2005US20050088874 Semiconductor memory having a spare memory cell
04/28/2005US20050088871 Semiconductor device and method of inspecting the same
04/28/2005US20050088869 Nonvolatile ferroelectric memory cell and memory device using the same
04/28/2005US20050088788 Magnetoresistive effect element and magnetic memory having the same
04/28/2005US20050088383 Methods and apparatus for selectively updating memory cell arrays
04/28/2005US20050088219 Pass gate circuit with stable operation in transition phase of input signal, self-refresh circuit including the pass gate circuit, and method of controlling the pass gate circuit
04/28/2005US20050088211 Jitter suppressing delay locked loop circuits and related methods
04/28/2005US20050088200 Signal transmitting device suited to fast signal transmission
04/28/2005US20050087831 Semiconductor device formed on (111) surface of a Si crystal and fabrication process thereof
04/28/2005US20050087827 Thin film magnetic memory device and manufacturing method therefor
04/28/2005US20050087797 Semiconductor memory device
04/28/2005US20050087786 Magnetic random access memory
04/28/2005US20050087785 Magnetic random access memory cell
04/28/2005US20050087749 Electroluminescent multilayer optical information storage medium with integrated readout and composition of matter for use therein
04/28/2005US20050087512 Ink jet printhead chip that incorporates through-wafer ink ejection mechanisms
04/28/2005US20050087511 Process for making magnetic memory structures having different-sized memory cell layers
04/27/2005EP1526588A1 Magnetoresistance effect element and magnetic memory unit
04/27/2005EP1526549A1 System and method of calibrating a read circuit in a magnetic memory
04/27/2005EP1526458A2 Column redundancy circuit with reduced signal path delay
04/27/2005EP1525584A2 Magnetoresistive random access memory with soft magnetic reference layer
04/27/2005EP1346366B1 A method for non-destructive readout and apparatus for use with the method
04/27/2005EP1340229B1 Integrated memory with an arrangement of non-volatile memory cells and method for the production and operation of an integrated memory
04/27/2005CN1610976A Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
04/27/2005CN1610951A Method and apparatus to program a phase change memory
04/27/2005CN1610949A Writing to a scalable MRAM element
04/27/2005CN1610947A Method and architecture for refreshing a 1t memory proportional to temperature
04/27/2005CN1610262A Jitter suppressing delay locked loop circuits and related methods
04/27/2005CN1610116A Ferroelectric material, ferroelectric film and method of manufacturing the same, ferroelectric capacitor and method of manufacturing the same, ferroelectric memory,
04/27/2005CN1610109A Stacked semiconductor device and semiconductor chip control method
04/27/2005CN1610005A Semiconductor memory device and flat panel display using the same
04/27/2005CN1610004A Clock signal synchronizer and clock signal synchronizing method
04/27/2005CN1610003A Level converter
04/27/2005CN1610002A Semiconductor memory device with proper sensing timing
04/27/2005CN1610001A Semiconductor memory device with magnetoresistance elements and method of writing data into the same
04/27/2005CN1610000A Magnetoresistive element, magnetic memory cell, and magnetic memory device
04/27/2005CN1199278C Element using magnetic material and addressing method therefor
04/27/2005CN1199274C Semiconductor storage device
04/27/2005CN1199193C A read-only memory and read-only memory device
04/27/2005CN1199192C A read-only memory and read-only memory devices
04/27/2005CN1199191C Integrated circuit with improved chip external drivers
04/27/2005CN1199190C Memory with word line voltage control and testing method thereof
04/27/2005CN1199187C Semiconductor memory device
04/27/2005CN1199186C Thin film magnetic storaging apparatus having storing unit with magnetic tunnel joint part
04/27/2005CN1199185C Integrated storage with storage unit having magnetic resistance storage effect
04/27/2005CN1199184C MTJ stack type unit storage detecting method and device
04/27/2005CN1199182C Semiconductor storage adopting reductant mode
04/26/2005US6886105 Method and apparatus for resuming memory operations from a low latency wake-up low power state
04/26/2005US6886076 Semiconductor integrated circuit device having connection pads for superposing expansion memory
04/26/2005US6886072 Control device for semiconductor memory device and method of controlling semiconductor memory device
04/26/2005US6885609 Semiconductor memory device supporting two data ports
04/26/2005US6885608 Multi-port memory circuit
04/26/2005US6885606 Synchronous semiconductor memory device with a plurality of memory banks and method of controlling the same
04/26/2005US6885605 Power-up signal generator for semiconductor memory devices
04/26/2005US6885603 Dynamic random access memory devices and method of controlling refresh operation thereof
04/26/2005US6885600 Differential sense amplifier for multilevel non-volatile memory
04/26/2005US6885598 Shared sense amplifier scheme semiconductor memory device and method of testing the same
04/26/2005US6885593 Semiconductor device
04/26/2005US6885591 Packet buffer circuit and method
04/26/2005US6885583 Nonvolatile semiconductor memory