| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 06/28/1995 | EP0660222A1 Data converter with fifo |
| 06/28/1995 | EP0396669B1 Method and apparatus for detecting impending overflow and/or underrun of elasticity buffer |
| 06/27/1995 | US5428801 Data array conversion control system for controlling conversion of data arrays being transferred between two processing systems |
| 06/27/1995 | US5428627 Method and apparatus for initializing an ECC circuit |
| 06/20/1995 | US5426784 Serial to parallel data converting circuit |
| 06/20/1995 | US5426780 System for dynamic segmentation analysis using conversion of relational data into object-oriented data |
| 06/20/1995 | US5426756 Memory controller and method determining empty/full status of a FIFO memory using gray code counters |
| 06/20/1995 | US5426639 Multiple virtual FIFO arrangement |
| 06/20/1995 | US5426612 First-in first-out semiconductor memory device |
| 06/20/1995 | US5426379 Field programmable gate array with built-in bitstream data expansion |
| 06/14/1995 | EP0658019A1 Method and device for generation of clock signals |
| 06/14/1995 | EP0657805A1 Result normalizer and method of operation |
| 06/13/1995 | US5424967 Shift and rounding circuit and method |
| 06/13/1995 | US5424732 Transmission compatibility using custom compression method and hardware |
| 06/06/1995 | US5423010 Structure and method for packing and unpacking a stream of N-bit data to and from a stream of N-bit data words |
| 06/01/1995 | DE4437790A1 Channel modulation process for finite state machine with error correction and entropy coding |
| 05/31/1995 | EP0655691A1 Processor interface circuit for exchanging serial digital data with a peripheral device |
| 05/31/1995 | EP0655675A1 Shift and rounding circuit and method |
| 05/30/1995 | US5420894 Phase synchronization circuit for use in a telephone system |
| 05/27/1995 | CA2136560A1 Method and device for generation of clock signals |
| 05/23/1995 | US5418913 System of two-way communication between processors using a single queue partitioned with pointers and limited overwrite privileges |
| 05/16/1995 | US5416749 Electronic storage apparatus |
| 05/16/1995 | US5416731 High-speed barrel shifter |
| 05/03/1995 | EP0651334A1 Data transfer in a data processing system |
| 05/03/1995 | EP0651329A2 Frame buffering of network packets |
| 05/03/1995 | EP0651319A1 System for transferring data |
| 05/02/1995 | US5412611 FIFO memory device capable of writing contiguous data into rows |
| 05/02/1995 | US5412610 Serial data transfer device |
| 05/02/1995 | US5412384 In a computer-implemented system |
| 04/29/1995 | CA2134061A1 Frame buffering of network packets |
| 04/26/1995 | EP0650264A1 Byte aligned data compression |
| 04/25/1995 | US5410722 Queue system for dynamically allocating and moving memory registers between a plurality of pseudo queues |
| 04/25/1995 | US5410677 Apparatus for translating data formats starting at an arbitrary byte position |
| 04/20/1995 | WO1995010897A1 A buffering method and a buffer |
| 04/19/1995 | EP0588921A4 Data compression using multiple levels. |
| 04/11/1995 | US5406554 Data switching system |
| 04/11/1995 | US5406518 Variable length delay circuit utilizing an integrated memory device with multiple-input and multiple-output configuration |
| 04/11/1995 | US5406282 Data coding and decoding with improved efficiency |
| 04/06/1995 | WO1995009398A1 System for transmitting intranodal command instructions or internodal communications in a processor node |
| 04/05/1995 | EP0646871A2 Data transfer control system |
| 04/04/1995 | US5404452 Personal computer bus and video adapter for high performance parallel interface |
| 04/04/1995 | US5404332 Apparatus for and a method of detecting a malfunction of a FIFO memory |
| 03/29/1995 | EP0645775A1 Electronic sequential access memory circuit |
| 03/29/1995 | EP0645696A1 Semiconductor memory device using serial pointer |
| 03/29/1995 | EP0645065A1 Method and equipment for monitoring the fill rate of an elastic buffer memory in a synchronous digital telecommunication system |
| 03/23/1995 | WO1995006285A3 Read and write data aligner and device utilizing same |
| 03/22/1995 | EP0644478A2 Fill level indicator for self-timed F.I.-F.O. |
| 03/15/1995 | EP0643491A1 Method and system for data compression |
| 03/14/1995 | US5398328 System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory orders |
| 03/14/1995 | US5398209 Serial access memory with column address counter and pointers |
| 03/14/1995 | US5398027 Decoding circuit for variable length code |
| 03/07/1995 | US5396460 FIFO memory in which number of bits subject to each data read/write operation is changeable |
| 03/02/1995 | WO1995006285A2 Read and write data aligner and device utilizing same |
| 03/01/1995 | EP0640912A1 Memory addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers |
| 03/01/1995 | EP0640910A1 Control process for a first in - first out circuit and device to carry it out |
| 03/01/1995 | EP0616744A4 Digital clock dejitter circuits for regenerating clock signals with minimal jitter. |
| 02/28/1995 | US5394399 Communication control system |
| 02/21/1995 | US5392412 Data communication controller for use with a single-port data packet buffer |
| 02/21/1995 | US5392406 DMA data path aligner and network adaptor utilizing same |
| 02/21/1995 | US5392366 Pattern recognition apparatus |
| 02/21/1995 | US5392318 Method and apparatus for deskewing/resynchronizing data slices with variable skews |
| 02/21/1995 | US5392228 Result normalizer and method of operation |
| 02/15/1995 | EP0639014A1 Access control method for a buffer store and apparatus for buffering data packets and switching node using said apparatus |
| 02/15/1995 | EP0510116A4 Method and apparatus for providing maximum rate modulation or compression encoding and decoding |
| 02/14/1995 | US5389924 Multiple character code set input/output conversion system |
| 02/14/1995 | US5389922 Compression using small dictionaries with applications to network packets |
| 02/07/1995 | US5388074 FIFO memory using single output register |
| 01/31/1995 | US5386585 Parallel processing system |
| 01/31/1995 | US5386532 Method and apparatus for transferring data between a memory and a plurality of peripheral units through a plurality of data channels |
| 01/31/1995 | US5386513 Self filling and emptying data pipeline |
| 01/31/1995 | US5386419 Multiplexer for at least two independently operating signal sources |
| 01/31/1995 | US5386390 Semiconductor memory with looped shift registers as row and column drivers |
| 01/25/1995 | EP0635818A1 Method and apparatus for efficient transfer of data to memory |
| 01/25/1995 | EP0635782A1 Method and system for address access |
| 01/24/1995 | US5384744 Look ahead flag for FIFO |
| 01/24/1995 | US5384723 Method and apparatus for floating point normalization |
| 01/24/1995 | US5384567 Combination parallel/serial execution of sequential algorithm for data compression/decompression |
| 01/14/1995 | CA2127831A1 Method of controlling access to a buffer as well as apparatus for temporarily storing data packets and exchange with such apparatus |
| 01/11/1995 | EP0633668A2 Data compression apparatus |
| 01/10/1995 | US5381528 Demand allocation of read/write buffer partitions favoring sequential read cache |
| 01/10/1995 | US5381360 Modulo arithmetic addressing circuit |
| 01/10/1995 | US5381126 Programmable difference flag logic |
| 01/09/1995 | CA2122170A1 Combination parallel/serial execution of sequential algorithm for data compression/decompression |
| 01/03/1995 | US5379399 FIFO memory controller for a digital video communications channel having a detector, comparator, and threshold select logic circuit |
| 01/03/1995 | US5379240 Shifter/rotator with preconditioned data |
| 12/31/1994 | CA2126173A1 Method and apparatus for efficient transfer of data to memory |
| 12/21/1994 | EP0629303A1 Apparatus, system and method for facilitating communication between components having different byte orderings |
| 12/20/1994 | US5375208 Device for managing a plurality of independent queues in a common non-dedicated memory space |
| 12/20/1994 | US5375092 First-in first-out memory device |
| 12/13/1994 | US5373204 Self-timed clocking transfer control circuit |
| 12/06/1994 | US5371877 Apparatus for alternatively accessing single port random access memories to implement dual port first-in first-out memory |
| 12/06/1994 | US5371684 Semiconductor floor plan for a register renaming circuit |
| 11/29/1994 | US5369508 Information processing methodology |
| 11/24/1994 | WO1994015269A3 Apparatus, system and method for facilitating communication between components having different byte orderings |
| 11/22/1994 | US5367643 Generic high bandwidth adapter having data packet memory configured in three level hierarchy for temporary storage of variable length data packets |
| 11/22/1994 | US5367638 Digital data processing circuit with control of data flow by control of the supply voltage |
| 11/22/1994 | US5367534 Synchronous flow control method |
| 11/22/1994 | US5367299 Method for 5-bit chunk encoding of bit serial data by a data processor handling data in 8-bit byte segments |
| 11/15/1994 | US5365485 Fifo with fast retransmit mode |
| 11/09/1994 | EP0623877A2 System and method for storing persistent and non-persistent queued data |