| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 02/23/2005 | CN1190727C Element testing and switching device |
| 02/16/2005 | EP1507212A1 Information processing apparatus, information processing method, content distributing apparatus, content distributing method, and computer program |
| 02/16/2005 | CN1581127A Integrated circuit and information processing apparatus |
| 02/15/2005 | US6857043 Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter |
| 02/15/2005 | US6856270 Pipeline array |
| 02/15/2005 | CA2308648C Method to control data reception buffers for packetized voice channels |
| 02/10/2005 | WO2005013639A2 Buffer management system, digital audio receiver, headphones, loudspeaker, method of buffer management |
| 02/10/2005 | US20050033907 Overflow protected first-in first-out architecture |
| 02/10/2005 | US20050033875 System and method for selectively affecting data flow to or from a memory device |
| 02/09/2005 | EP1505500A2 Integrated circuit and information processing apparatus |
| 02/09/2005 | EP1505489A1 Overflow protected first-in first-out architecture |
| 02/09/2005 | EP1149472B1 Gray-code counter having a binary incrementer and method of operating the same |
| 02/09/2005 | CN1577257A SIMD integer multiply high with round and shift |
| 02/08/2005 | US6853699 High speed shifter circuit |
| 02/08/2005 | US6853390 Displaying option information using a non-modal dialog box |
| 02/03/2005 | US20050027777 High speed low power 4-2 compressor |
| 02/03/2005 | US20050024241 Method and apparatus for generating gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's |
| 02/03/2005 | US20050024120 Method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect |
| 02/03/2005 | US20050023518 Superconducting digital first-in first-out buffer using physical back pressure mechanism |
| 02/02/2005 | CN1574099A Bidirectional shift register and display device incorporating same |
| 02/02/2005 | CN1573675A 数据处理装置和移动装置 The data processing apparatus and the mobile apparatus |
| 02/01/2005 | US6850092 Low latency FIFO circuits for mixed asynchronous and synchronous systems |
| 01/27/2005 | WO2005008472A1 System and method for buffering variable-length data |
| 01/27/2005 | WO2004053680A3 Configurable memory partitioning in hardware |
| 01/27/2005 | US20050022067 Method for storing or transferring data |
| 01/27/2005 | US20050021929 Micro controller for processing compressed codes |
| 01/27/2005 | US20050018514 Integrated DDR/SDR flow control managers that support multiple queues and mux, demux and broadcast operating modes |
| 01/27/2005 | US20050017753 Scalable gray code counter |
| 01/27/2005 | US20050017065 Bidirectional shift register and display device incorporating same |
| 01/27/2005 | DE19983589B4 Hochfrequenz-Pipeline-Entkopplungswarteschlangengestaltung High-frequency decoupling pipeline queue design |
| 01/27/2005 | DE10330328A1 Processing method for data in a mixed-timing system, whereby a third clock signal is formed from the second data processing clock signal by application of a delay and a test signal is generated based on signal flank positions |
| 01/26/2005 | EP1499951A1 Circuit, apparatus and method for storing audiovisual data |
| 01/26/2005 | EP1499950A2 Output rate change |
| 01/26/2005 | CN1571956A Data alignment between native and non-native shared data structures |
| 01/26/2005 | CN1571953A Galois field linear transformer |
| 01/26/2005 | CN1571951A FIFO memory devices having single data rate (sdr) and dual data rate (ddr) capability |
| 01/26/2005 | CN1570847A Digital signal processor applying skip type floating number operational method |
| 01/26/2005 | CN1570843A Circuit realization structure for concurrent low power dissipation software computing element |
| 01/25/2005 | US6848042 Integrated circuit and method of outputting data from a FIFO |
| 01/25/2005 | US6847558 Integrated circuit and method of reading data from a memory device |
| 01/20/2005 | WO2005006195A2 System and method for selectively affecting data flow to or from a memory device |
| 01/20/2005 | WO2005006177A1 Frequency translation techniques |
| 01/20/2005 | WO2004092945A3 Data processing in which concurrently executed processes communicate via a fifo buffer |
| 01/20/2005 | US20050015733 System of hardware objects |
| 01/20/2005 | US20050014494 System and method for processing extensible markup language (XML) documents |
| 01/20/2005 | US20050013395 Data buffer-controlled digital clock regenerator |
| 01/19/2005 | EP1497006A1 Authentication in a secure computerized gaming system |
| 01/19/2005 | CN1568455A Method and apparatus for flexible data types |
| 01/18/2005 | US6845274 Communication port control module for lighting systems |
| 01/18/2005 | US6844834 Processor, encoder, decoder, and electronic apparatus |
| 01/18/2005 | US6844833 Methods and apparatus for constant-weight encoding and decoding |
| 01/13/2005 | WO2005003956A1 Single memory with multiple shift register functionality |
| 01/13/2005 | WO2005003955A2 Sequential flow-control and fifo memory devices that are depth expandable in standard mode operation |
| 01/13/2005 | WO2003101024A8 Symbol message methods, displays, games, and apparatuses |
| 01/13/2005 | US20050010701 Frequency translation techniques |
| 01/13/2005 | DE10324014A1 Adressgenerator, Betriebsverfahren dafür und diesen verwendendes Daten verarbeitendes System Address generator, operating method therefor, and such-use data-processing system |
| 01/12/2005 | CN1564975A Method and apparatus for buffer storage of data packets which are to be transmitted via a connection that has been set up |
| 01/11/2005 | US6842850 DSP data type matching for operation using multiple functional units |
| 01/11/2005 | US6842800 System and method for managing configurable buffer sizes |
| 01/06/2005 | US20050005250 Data interface for hardware objects |
| 01/06/2005 | US20050005082 Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation |
| 01/06/2005 | US20050005051 Circuit and method for aligning data transmitting timing of a plurality of lanes |
| 01/04/2005 | US6839889 Mixed hardware/software architecture and method for processing xDSL communications |
| 01/04/2005 | US6839863 Input data processing circuit comprising of a readout circuit for selecting one of first and second FIFO buffers having a faster clock |
| 01/04/2005 | US6839830 Logical pipeline for data communications system |
| 01/04/2005 | US6839360 FIFO storage including pointer misalignment detection |
| 12/30/2004 | US20040267994 Flexibility of design of a bus interconnect block for a data processing apparatus |
| 12/30/2004 | US20040267857 SIMD integer multiply high with round and shift |
| 12/30/2004 | US20040267710 Method for compressing a hierarchical tree, corresponding signal and method for decoding a signal |
| 12/29/2004 | WO2004114166A2 Integrated circuit development system |
| 12/29/2004 | WO2003107172A3 Fifo-register |
| 12/29/2004 | WO2003104968A3 Spacecake coprocessor communication |
| 12/29/2004 | EP1491995A2 first-in-first-out memory |
| 12/29/2004 | CA2527970A1 Integrated circuit development system |
| 12/28/2004 | US6836854 DS3 Desynchronizer with a module for providing uniformly gapped data signal to a PLL module for providing a smooth output data signal |
| 12/28/2004 | US6836809 Writing and reading data from a queue |
| 12/28/2004 | US6836521 Apparatus and method for generating a distributed clock signal using gear ratio techniques |
| 12/23/2004 | US20040260903 Ping-pong buffer system having a buffer to store a subset of data from a data source |
| 12/23/2004 | US20040260890 P-and v-semaphore operation |
| 12/23/2004 | US20040260888 Efficient fifo communication using semaphores |
| 12/23/2004 | US20040257856 Dual-port functionality for a single-port cell memory device |
| 12/23/2004 | DE4497707B4 Pufferungsverfahren und Puffer Pufferungsverfahren and buffers |
| 12/23/2004 | DE10324049A1 Integrierte Schaltung und Verfahren zum Betreiben der integrierten Schaltung Integrated circuit and method for operating the integrated circuit |
| 12/22/2004 | EP1316220B1 Method for compressing/decompressing structured documents |
| 12/22/2004 | CN1181431C Input data processing circuit |
| 12/21/2004 | US6834293 Vector scaling system for G.728 annex G |
| 12/16/2004 | WO2004109523A2 Method and apparatus for enhancing the speed of a synchronous bus |
| 12/16/2004 | WO2004044731A3 Device and method for performing shift/rotate operations |
| 12/16/2004 | US20040255284 Compiler |
| 12/16/2004 | US20040255227 Method and apparatus for buffer storage of data packets which are to be transmitted via a connection that has been set up |
| 12/16/2004 | US20040255188 Method and apparatus for determining a status of an asynchronous memory |
| 12/16/2004 | US20040255070 Inter-integrated circuit router for supporting independent transmission rates |
| 12/16/2004 | US20040251954 Flexibility of use of a data processing apparatus |
| 12/15/2004 | EP1034538B1 Transferring compressed audio via a playback buffer |
| 12/14/2004 | US6832234 In-place associative processor arithmetic |
| 12/09/2004 | US20040250002 Accessory control interface |
| 12/09/2004 | US20040250000 Method and device for linking work requests with completion queue entries |
| 12/09/2004 | US20040249997 System and method for communicating data |
| 12/09/2004 | US20040249981 Method and circuit for transmitting data from a system which is operated by means of a first clock to a system which is operated by means of a second clock pulse |
| 12/09/2004 | US20040249964 Method of data transfer and apparatus therefor |