Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled
Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116)
08/2005
08/24/2005CN1659508A Spacecake coprocessor communication
08/24/2005CN1658596A FIFO module, deskew circuit and rate matching circuit having the same
08/24/2005CN1658181A Conversion apparatus and method thereof
08/23/2005US6934729 Method and system for performing shift operations
08/23/2005US6934198 First-in, first-out buffer system in an integrated circuit
08/18/2005WO2005076123A1 Method and circuit for differential clock pulse compensation between two clock-pulse systems
08/18/2005US20050182809 Arithmetic circuits for use with the residue number system
08/18/2005US20050180250 Data packet buffering system with automatic threshold optimization
08/17/2005EP1563401A1 Data processing apparatus with address redirection in response to periodic address patterns
08/17/2005CN1656689A Packing and unpacking of a variable number of bits
08/16/2005US6931561 Apparatus and method for asynchronously interfacing high-speed clock domain and low-speed clock domain using a plurality of storage and multiplexer components
08/16/2005US6931426 Apparatus and method for detecting operation value using lookup-table
08/11/2005WO2005003955A3 Sequential flow-control and fifo memory devices that are depth expandable in standard mode operation
08/11/2005US20050177659 Spacecake coprocessor communication
08/11/2005US20050174268 Packing and unpacking for variable number of bits
08/10/2005CN1214335C Apparatus and method for processing data
08/09/2005US6928574 System and method for transferring data from a lower frequency clock domain to a higher frequency clock domain
08/09/2005US6928573 Communication clocking conversion techniques
08/04/2005US20050169390 Data processing apparatus and method and encoding device
08/03/2005EP0992906B1 Apparatus and method for software breakpoint in a delay slot
08/03/2005CN1213372C Data transmission controller, electronic machine and data transmission control method
08/02/2005US6925506 Architecture for implementing virtual multiqueue fifos
08/02/2005US6925014 Integrated circuit and method of reading data from a memory device
07/2005
07/28/2005WO2005069121A1 Electronic circuit with a fifo pipeline
07/28/2005US20050166032 Address generator for detecting and correcting read/write buffer overflow and underflow
07/27/2005EP1557976A1 Method and apparatus for multicasting of cell or frame data
07/27/2005EP1556753A1 Declarative markup for scoring multiple time-based assets and events within a scene composition system
07/27/2005EP1330700B1 Multiplier and shift device using signed digit representation
07/27/2005CN1647049A Pipelined parallel programming operation in a non-volatile memory system
07/27/2005CN1647026A Circuit, apparatus and method for storing audiovisual data
07/27/2005CN1647025A Method of and device for changing an output rate
07/26/2005US6922111 Adaptive frequency clock signal
07/21/2005WO2005066827A2 Buffer management via non-data symbol processing for a point to point link
07/21/2005US20050160245 Novel FIFO memory architecture and method for the management of the same
07/21/2005US20050160215 Flow through asynchronous elastic FIFO apparatus and method for implementing multi-engine parsing and authentication
07/21/2005US20050157719 Method and apparatus for multicasting of cell or frame data
07/21/2005DE102004059125A1 Vorrichtung und Verfahren zum Schreiben von Daten in einem Prozessor in den Speicher an einen unausgerichteten Ort Apparatus and method for writing data to a processor in the memory of a place unaligned
07/19/2005US6920578 Method and apparatus for transferring data between a slower clock domain and a faster clock domain in which one of the clock domains is bandwidth limited
07/14/2005US20050154843 Method of managing a device for memorizing data organized in a queue, and associated device
07/13/2005CN1640083A 附件控制接口 Accessories Control Interface
07/13/2005CN1639724A Method and system for detecting variances in a tracking environment
07/13/2005CN1639680A Shared queue for multiple input-streams
07/13/2005CN1639679A A communication system
07/12/2005US6918119 Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environments
07/07/2005US20050146950 Method and circuit for elastic storing capable of adapting to high-speed data communications
07/07/2005US20050146939 Pipelined parallel programming operation in a non-volatile memory system
07/05/2005US6915492 System for accessing a large number of menu items using a zoned menu bar
07/05/2005US6914471 Method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect
06/2005
06/30/2005US20050144567 System for accessing a large number of menu items using a zoned menu bar
06/30/2005US20050144341 Buffer management via non-data symbol processing for a point to point link
06/30/2005US20050144214 Shift-and-negate unit within a fused multiply-adder circuit
06/30/2005US20050140310 Intelligent electrical switching device
06/29/2005EP1546930A1 Programmable streaming data processor for database appliance having multiple processing unit groups
06/29/2005EP1546928A1 Field oriented pipeline architecture for a programmable data streaming processor
06/29/2005EP1546926A1 Asymmetric streaming record data processor method and apparatus
06/29/2005EP1546863A1 Computationally efficient mathematical engine
06/29/2005EP1546858A1 Apparatus and method for dynamic program decompression
06/29/2005EP1546822A2 Asymmetric data streaming architecture having autonomous and asynchronous job processing unit
06/28/2005US6912566 Memory device and method for operating the memory device
06/28/2005US6912057 Image forming apparatus and image forming method
06/23/2005WO2005057861A1 Data collection system
06/23/2005WO2004059471A3 Clock skew compensation apparatus and method
06/23/2005US20050138459 Method and apparatus for controlling amount of buffer data in a receiver of a data communication system, and method and apparatus for playing streaming data with adaptive clock synchronization unit
06/23/2005US20050138344 Device and method for writing data in a processor to memory at unaligned location
06/23/2005US20050135159 FIFO control circuit
06/22/2005EP1544724A1 New FIFO memory structure and operting procedure of such a memory
06/21/2005US6910084 Method and system for transferring and storing data in a medical device with limited storage and memory
06/21/2005US6909109 Superconducting digital first-in first-out buffer using physical back pressure mechanism
06/16/2005US20050128846 Methods and circuitry for implementing first-in first-out structure
06/16/2005US20050128834 Data transfer circuit having collision detection circuit
06/15/2005EP1542131A1 Method of managing a storage organised as FIFO, and corresponding apparatus
06/15/2005EP1540507A2 Methods and devices for treating and/or processing data
06/15/2005CN1627280A Data transfer circuit
06/14/2005US6907541 System for recovering received data with a reliable gapped clock signal after reading the data from memory using enable and local clock signals
06/14/2005US6907479 Integrated circuit FIFO memory devices that are divisible into independent FIFO queues, and systems and methods for controlling same
06/14/2005US6907452 Method and apparatus for attaching viewer applets to electronic mail communications
06/14/2005US6906644 Encoding and decoding apparatus with matching length means for symbol strings
06/09/2005US20050122971 System and method for buffering variable-length data
06/09/2005US20050122823 Methods and apparatus for constant-weight encoding and decoding
06/09/2005US20050122815 Methods and circuitry for implementing first-in first-out structure
06/09/2005US20050122794 First-in first-out memory system with shift register fill indication
06/09/2005US20050122793 First-in first-out memory system with single bit collision detection
06/08/2005CN1205574C Method of anda pparauts for compressing and expanding data
06/07/2005US6904596 Method and apparatus for shared flow control of data
06/07/2005US6904539 Method of determining data transfer speed in data transfer apparatus
06/07/2005US6904447 High speed low power 4-2 compressor
06/02/2005US20050117428 Methods and circuitry for implementing first-in first-out structure
06/02/2005DE102004011673B3 Data synchronization device for exchange of clocked data between different clock regions in data processor uses buffer memory with write-in selection multiplexer and read-out selection multiplexer synchronized with respective clocks
06/01/2005EP1535149A2 Method and apparatus for downloading executable code in a non-disruptive manner
05/2005
05/31/2005US6901528 Minimum latency propagation of variable pulse width signals across clock domains with variable frequencies
05/31/2005US6901463 Method and device for linking work requests with completion queue entries
05/31/2005US6901420 Method and apparatus for performing packed shift operations
05/31/2005US6900745 Method of scalable gray coding
05/26/2005WO2005024542A3 Digital signal processing device
05/26/2005US20050114419 Discrete cosine transformation apparatus, inverse discrete cosine transformation apparatus, and orthogonal transformation apparatus
05/26/2005US20050111292 Storage device for storing data while compressing same value of input data
05/25/2005EP1068569B1 Device and method for buffer protection
05/25/2005CN1203387C Method for regulating character frequency
05/24/2005US6898742 System and method for automatic deskew across a high speed, parallel interconnection
05/24/2005US6898613 Arithmetic circuits for use with the residue number system
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