Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
10/2000
10/31/2000US6140856 Parametric tuning of an intergrated circuit after fabrication
10/31/2000US6140855 Dynamic-latch-receiver with self-reset pointer
10/31/2000US6140848 Electronic driver circuit that utilizes resonance with load circuitry in combination with timed switching to reduce power consumption
10/31/2000US6140846 Driver circuit configured for use with receiver
10/31/2000US6140842 Differential, high speed, ECL to CMOS converter
10/31/2000US6140840 Macro cell signal selector and semiconductor integrated circuit including these parts
10/31/2000US6140839 Computational field programmable architecture
10/31/2000US6140838 High density and high speed magneto-electronic logic family
10/31/2000US6140835 Input buffer circuit
10/31/2000US6140834 Semiconductor integrated circuit
10/26/2000DE19961061A1 Semiconductor device for switching has silicon on insulator construction with MOS transistor circuit configuration
10/26/2000DE19936606C1 Integrated circuit voltage supply via pad e.g. for microprocessors and microcontrollers
10/26/2000DE19930183C1 Signal level conversion, self-calibrating CMOS circuit e.g. for mobile radio applications
10/25/2000EP1047194A1 High-frequency clipping stage
10/25/2000CN1271464A Electrode means, with or without functional elements and an electrode device including polymer material and an electrode device formed of saidmeans
10/24/2000US6138205 Burst mode type semiconductor memory device
10/24/2000US6138177 System and method of pin programming and configuration
10/24/2000US6137728 Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor
10/24/2000US6137342 High efficiency semiconductor substrate bias pump
10/24/2000US6137339 High voltage integrated CMOS driver circuit
10/24/2000US6137322 Dynamic output control circuit
10/24/2000US6137320 Input receiver circuit
10/24/2000US6137318 Logic circuit having dummy MOS transistor
10/24/2000US6137317 CMOS driver
10/24/2000US6137316 Integrated circuit with improved off chip drivers
10/24/2000US6137314 Input circuit for an integrated circuit
10/24/2000US6137313 Resistive pull-up device for I/O pin
10/24/2000US6137312 Voltage level translator
10/24/2000US6137311 Failsafe interface circuit
10/24/2000US6137309 Exclusive-or logic gate with four two-by-two complementary inputs and two complementary outputs, and frequency multiplier incorporating said gate
10/24/2000US6137308 Programmable interconnect matrix architecture for complex programmable logic device
10/24/2000US6137307 Structure and method for loading wide frames of data from a narrow input bus
10/24/2000US6137306 Input buffer having adjustment function for suppressing skew
10/19/2000WO2000062311A1 Magnetic materials
10/19/2000CA2366588A1 Magnetic materials
10/18/2000EP1045446A2 MOS invertor having a constricted channel width
10/18/2000EP1010013A4 Impedance control circuit
10/18/2000CN1057648C Differential amplifying apparatus
10/17/2000US6134679 System and method for accessing devices in a computer system
10/17/2000US6134672 System and method for iterative copying of read/write memory
10/17/2000US6134173 Programmable logic array integrated circuits
10/17/2000US6134171 Semiconductor integrated circuit device having hierarchical power source arrangement
10/17/2000US6134166 Programmable logic array integrated circuit incorporating a first-in first-out memory
10/17/2000US6133767 Digital driver circuit for an integrated circuit
10/17/2000US6133762 Family of logic circuits emploting mosfets of differing thershold voltages
10/17/2000US6133761 Logic circuit
10/17/2000US6133759 Decoupled reset dynamic logic circuit
10/17/2000US6133758 Selectable self-timed replacement for self-resetting circuitry
10/17/2000US6133757 High-speed and low-noise output buffer
10/17/2000US6133756 Output buffer control circuit
10/17/2000US6133755 Input/output buffer with reduced ring-back effect
10/17/2000US6133754 Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC)
10/17/2000US6133752 Semiconductor integrated circuit having tri-state logic gate circuit
10/17/2000US6133751 Programmable delay element
10/17/2000US6133750 Combination of global clock and localized clocks
10/17/2000US6133749 Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance
10/17/2000US6133748 Crow-bar current reduction circuit
10/17/2000US6133747 Time redundant radiation tolerant logic
10/12/2000DE10001733A1 Power supply control device has processing device with information provided through an AC adapter supplied via external power through battery
10/11/2000EP1042868A1 A voltage translator circuit which allows for variable low voltage signal translation
10/10/2000US6131073 Electronic circuit with an operating characteristic correcting function
10/10/2000US6130854 Programmable address decoder for field programmable memory array
10/10/2000US6130842 Adjustable verify and program voltages in programmable devices
10/10/2000US6130812 Protection circuit for high speed communication
10/10/2000US6130584 Over-sampling type clock recovery circuit with power consumption reduced
10/10/2000US6130575 High-speed switching regulator drive circuit
10/10/2000US6130569 Method and apparatus for a controlled transition rate driver
10/10/2000US6130559 QMOS digital logic circuits
10/10/2000US6130558 Data transfer circuit and method for a semiconductor memory
10/10/2000US6130557 Three level pre-buffer voltage level shifting circuit and method
10/10/2000US6130556 Integrated circuit I/O buffer with 5V well and passive gate voltage
10/10/2000US6130555 Driver circuitry for programmable logic devices
10/10/2000US6130554 Programmable integrated circuit having a test circuit for testing the integrity of routing resource structures
10/10/2000US6130553 Programmable function block
10/10/2000US6130552 Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution
10/10/2000US6130551 Synthesis-friendly FPGA architecture with variable length and variable timing interconnect
10/10/2000US6130550 Scaleable padframe interface circuit for FPGA yielding improved routability and faster chip layout
10/10/2000US6130549 Output driver of an integrated semiconductor chip
10/05/2000WO2000058807A1 Manipulation-proof integrated circuit
10/04/2000EP1041719A1 Circuit for dynamic switching of a buffer threshold
10/04/2000EP1041718A2 A low power adjustable input threshold circuit
10/04/2000EP1041571A2 Dynamic-latch-receiver with self-reset pointer
10/04/2000EP1041482A1 Tamperproof integrated circuit
10/04/2000EP1040580A1 Cmos output amplifier independent of temperature, supply voltage and manufacturing quality of transistors
10/04/2000EP0895638B1 High reliability logic circuit for a radiation environment
10/04/2000CN1269028A Interface circuit for full-custom and semi-custom timing domains
10/03/2000US6128770 Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block)
10/03/2000US6128692 Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices
10/03/2000US6128356 CMOS circuit composed of CMOS circuit blocks arranged in bit-parallel data paths
10/03/2000US6127878 Driver circuit with negative lower power rail
10/03/2000US6127876 Positive ground bounce compensation circuit for bipolar integrated devices
10/03/2000US6127874 Skew adjustable IC and a method for designing the same
10/03/2000US6127862 Programmable impedance circuit
10/03/2000US6127861 Duty cycle adaptive data output buffer
10/03/2000US6127857 Output buffer or voltage hold for analog of multilevel processing
10/03/2000US6127850 Low power clock buffer with shared, clocked transistor
10/03/2000US6127849 Simultaneous bi-directional input/output (I/O) circuit
10/03/2000US6127848 Voltage translator with gate oxide breakdown protection
10/03/2000US6127847 High-speed bipolar-to-CMOS logic converter circuit
10/03/2000US6127846 Programmable logic array devices with interconnect lines of various lengths