| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 06/05/2001 | US6242940 Data input buffer circuit |
| 06/05/2001 | US6242939 Superconducting circuit having superconductive circuit device of voltage-type logic and superconductive circuit device of fluxoid-type logic device selectively used therein |
| 06/05/2001 | US6242821 CMOS passive input circuit |
| 05/31/2001 | WO2001039376A1 Programmable logic device and programming method |
| 05/31/2001 | WO2001039373A1 Improved voltage translator circuit |
| 05/31/2001 | WO2001039251A2 High performance output buffer with esd protection |
| 05/31/2001 | WO2001039249A2 Universal hardware device and method and tools for use therewith |
| 05/31/2001 | WO1999048260A9 High speed signaling for interfacing vlsi cmos circuits |
| 05/30/2001 | CN2432731Y Power supply voltage detecting circuit |
| 05/30/2001 | CN1297638A High speed signaling for interfacing VLSI CMOS circuits |
| 05/29/2001 | USRE37195 Programmable switch for FPGA input/output signals |
| 05/29/2001 | US6240536 Scanable latch circuit and method for providing a scan output from a latch circuit |
| 05/29/2001 | US6240438 Multiplier circuit for reducing the number of necessary elements without sacrificing high speed capability |
| 05/29/2001 | US6240035 Semiconductor integrated circuit device and method of activating the same |
| 05/29/2001 | US6239956 Fail-safe timing circuit and on-delay circuit using the same |
| 05/29/2001 | US6239649 Switched body SOI (silicon on insulator) circuits and fabrication method therefor |
| 05/29/2001 | US6239644 Clock stretcher and level shifter with small component count and low power consumption |
| 05/29/2001 | US6239639 Latch circuit |
| 05/29/2001 | US6239623 Direct coupling field effect transistor logic (DCFL) circuit |
| 05/29/2001 | US6239622 Self-timed domino circuit |
| 05/29/2001 | US6239621 Two legged reset controller for domino circuit |
| 05/29/2001 | US6239618 Buffer with fast edge propagation |
| 05/29/2001 | US6239617 Mixed voltage output driver with automatic impedance adjustment |
| 05/29/2001 | US6239616 Programmable delay element |
| 05/29/2001 | US6239615 High-performance interconnect |
| 05/29/2001 | US6239614 Semiconductor integrated circuit device |
| 05/29/2001 | US6239613 Tristate structures for programmable logic devices |
| 05/29/2001 | US6239612 Programmable I/O cells with multiple drivers |
| 05/29/2001 | CA2173034C Bimos integrated circuit |
| 05/25/2001 | WO2001037322A2 System and method for product yield prediction using a logic characterization vehicle |
| 05/23/2001 | EP1102446A2 Digital signal transmission circuit |
| 05/23/2001 | EP1102402A1 Level adjustment circuit and data output circuit thereof |
| 05/23/2001 | EP1102401A1 Bus driver circuit and method for operating the same |
| 05/23/2001 | EP1101286A1 A level converter provided with slew-rate controlling means |
| 05/23/2001 | DE19954889A1 Decoder element e.g. for word-line decoder of integrated store |
| 05/23/2001 | CN1066289C Electrostatic discharge circuit for high-speed, high-voltage circuit |
| 05/22/2001 | US6237131 Techniques and circuits for high yield improvements in programmable devices using redundant routing resources |
| 05/22/2001 | US6237107 Dynamic slew rate control output buffer |
| 05/22/2001 | US6236613 Semiconductor integrated circuit device having a hierarchical power source configuration |
| 05/22/2001 | US6236549 Circuit for preventing module damage in integrated circuits which require a plurality of supply voltages |
| 05/22/2001 | US6236257 Method and apparatus for reducing using feed forward compensation |
| 05/22/2001 | US6236256 Voltage level converters |
| 05/22/2001 | US6236255 Output impedance adjustment circuit |
| 05/22/2001 | US6236248 Output buffer circuit |
| 05/22/2001 | US6236245 Output pre-driver for reducing totem pole current |
| 05/22/2001 | US6236244 High voltage level shifter for driving an output stage |
| 05/22/2001 | US6236240 Hold-time latch mechanism compatible with single-rail to dual-rail conversion |
| 05/22/2001 | US6236239 Output buffer circuit achieving stable operation and cost reduction |
| 05/22/2001 | US6236238 Output buffer with independently controllable current mirror legs |
| 05/22/2001 | US6236237 Output buffer predriver with edge compensation |
| 05/22/2001 | US6236236 2.5 volt input/output buffer circuit tolerant to 3.3 and 5 volts |
| 05/22/2001 | US6236235 Output circuit |
| 05/22/2001 | US6236234 High-speed low-power consumption interface circuit |
| 05/22/2001 | US6236233 Method and system for translating TTL off-chip drive for integrated circuit with negative substrate bias |
| 05/22/2001 | US6236232 Multi-purpose transistor array |
| 05/22/2001 | US6236231 Programmable logic integrated circuit devices with low voltage differential signaling capabilities |
| 05/22/2001 | US6236230 Method, architecture and circuit for product term allocation |
| 05/22/2001 | US6236229 Integrated circuits which employ look up tables to provide highly efficient logic cells and logic functionalities |
| 05/17/2001 | WO2001035532A1 Integrated digital circuit and a method for operating same |
| 05/17/2001 | US20010001229 Semiconductor integrated circuit |
| 05/17/2001 | US20010001228 Input/output buffer capable of supporting a multiple of transmission logic buses |
| 05/17/2001 | DE10056396A1 Waveform shaping circuit has simultaneous line stages between input, output nodes, current mirror circuits, capacitance device coupled to mirror circuit(s) and output node |
| 05/16/2001 | EP1100199A2 Semiconductor device |
| 05/16/2001 | EP1099309A1 Apparatus and methods for high throughput self-timed domino circuits |
| 05/16/2001 | EP1099308A2 Driving circuit |
| 05/15/2001 | US6233707 Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clock |
| 05/15/2001 | US6233191 Field programmable memory array |
| 05/15/2001 | US6232893 Method and apparatus for programmably providing a power supply voltage to an integrated circuit |
| 05/15/2001 | US6232827 Transistors providing desired threshold voltage and reduced short channel effects with forward body bias |
| 05/15/2001 | US6232821 System for allowing below-ground and rail-to-rail input voltages |
| 05/15/2001 | US6232819 Semiconductor integrated circuit device and low-amplitude signal receiving method |
| 05/15/2001 | US6232814 Method and apparatus for controlling impedance on an input-output node of an integrated circuit |
| 05/15/2001 | US6232811 Circuit for controlling setup/hold time of semiconductor device |
| 05/15/2001 | US6232803 Tightly controlled output level CMOS-PECL driver |
| 05/15/2001 | US6232800 Differential sense amplifier circuit and dynamic logic circuit using the same |
| 05/15/2001 | US6232799 Method and apparatus for selectively controlling weak feedback in regenerative pass gate logic circuits |
| 05/15/2001 | US6232798 Self-resetting circuit timing correction |
| 05/15/2001 | US6232797 Integrated circuit devices having data buffer control circuitry therein that accounts for clock irregularities |
| 05/15/2001 | US6232795 Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same |
| 05/15/2001 | US6232794 Electronic circuit with automatic signal conversion |
| 05/15/2001 | US6232793 Switched backgate bias for FET |
| 05/15/2001 | US6232792 Terminating transmission lines using on-chip terminator circuitry |
| 05/15/2001 | US6232678 Electronic appliance |
| 05/15/2001 | US6231147 Data storage circuits using a low threshold voltage output enable circuit |
| 05/15/2001 | CA2171052C A tristatable output driver for use with 3.3 or 5 volt cmos logic |
| 05/15/2001 | CA2101559C Complementary logic input parallel (clip) logic circuit family |
| 05/10/2001 | WO2001033715A1 On-chip decoupling capacitor system with parallel fuse |
| 05/10/2001 | WO2001006651A3 Integrated semiconductor circuit |
| 05/10/2001 | US20010000951 Integrated circuit with multi-function controlled impedance output drivers |
| 05/10/2001 | US20010000950 Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits |
| 05/10/2001 | US20010000949 Integrated circuit memory devices having programmable output driver circuits therein |
| 05/10/2001 | DE10037973A1 Data output circuit has buffer stage containing pull-up and pull-down transistors, high and low level data output control stages and substrate potential switching stage |
| 05/10/2001 | DE10026900A1 Passive CMOS-Eingangsschaltung Passive CMOS input circuit |
| 05/10/2001 | DE10024705A1 Pegelwandelverfahren und Pegelwandelschaltung Level conversion method and level conversion circuit |
| 05/09/2001 | EP1097386A1 Adaptive driver with capacitive load sensing and method of operation |
| 05/09/2001 | EP0836767A4 Mos termination for low power signaling |
| 05/09/2001 | CN1294783A Semiconductor integrated circuit device, recording medium stored with cell library, and method for designing semiconductor integrated circuit |
| 05/09/2001 | CN1294709A Circuit for powering down unused configuration bits to minimize power consumption |
| 05/09/2001 | CN1294452A High-speed low-noise output buffer |
| 05/09/2001 | CN1294451A Signal conversion circuit with dynamically regulated reference voltage and crystal chip set using it |