| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 04/17/2001 | US6218876 Phase-locked loop circuitry for programmable logic devices |
| 04/17/2001 | US6218867 Pass transistor circuit |
| 04/17/2001 | US6218864 Structure and method for generating a clock enable signal in a PLD |
| 04/17/2001 | US6218863 Dual mode input/output interface circuit |
| 04/17/2001 | US6218860 Programmable logic array integrated circuit incorporating a first-in first-out memory |
| 04/17/2001 | US6218859 Programmable logic device having quadrant layout |
| 04/17/2001 | US6218858 Programmable input/output circuit for FPGA for use in TTL, GTL, GTLP, LVPECL and LVDS circuits |
| 04/17/2001 | US6218857 Variable sized line driving amplifiers for input/output blocks (IOBs) in FPGA integrated circuits |
| 04/17/2001 | US6218856 High speed programmable logic architecture |
| 04/17/2001 | US6218854 Data line termination circuits and integrated circuit devices including attenuation circuit and charge/discharge circuit |
| 04/17/2001 | US6218713 Logical circuit, flip-flop circuit and storage circuit with multivalued logic |
| 04/17/2001 | US6218706 Integrated circuit with improved electrostatic discharge protection circuitry |
| 04/12/2001 | DE19946752A1 Rekonfigurierbares Gate-Array Reconfigurable gate array, |
| 04/12/2001 | CA2285882A1 Heterogeneous interconnection architecture for programmable logic devices |
| 04/11/2001 | EP1091492A1 An output buffer for digital signals |
| 04/11/2001 | EP1091491A1 Input buffer for integrated circuit |
| 04/11/2001 | EP0974082A4 Output buffer having a predriver for compensating slew rate against process variations |
| 04/10/2001 | US6216257 FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks |
| 04/10/2001 | US6216256 Semiconductor integrated circuit and method of designing the same |
| 04/10/2001 | US6216147 Method and apparatus for an N-nary magnitude comparator |
| 04/10/2001 | US6216146 Method and apparatus for an N-nary adder gate |
| 04/10/2001 | US6215875 Cipher processing system |
| 04/10/2001 | US6215349 Capacitive coupled driver circuit |
| 04/10/2001 | US6215344 Data transmission circuit |
| 04/10/2001 | US6215341 Deceleration circuit |
| 04/10/2001 | US6215340 Signal transition accelerating driver with simple circuit configuration and driver system using the same |
| 04/10/2001 | US6215339 Input buffer circuit |
| 04/10/2001 | US6215330 Differential diode transistor logic (DDTL) circuit enhancements |
| 04/10/2001 | US6215328 Buffer circuit with small delay |
| 04/10/2001 | US6215327 Molecular field programmable gate array |
| 04/10/2001 | US6215326 Programmable logic device architecture with super-regions having logic regions and a memory region |
| 04/10/2001 | US6215325 Implementing a priority function using ripple chain logic |
| 04/10/2001 | US6215170 Structure for single conductor acting as ground and capacitor plate electrode using reduced area |
| 04/10/2001 | US6215159 Semiconductor integrated circuit device |
| 04/10/2001 | CA2191634C Cmos sonet/atm receiver suitable for use with pseudo ecl and ttl signaling environments |
| 04/05/2001 | WO2001024466A1 Communication interface with terminated transmission lines |
| 04/05/2001 | WO2001024368A1 Reconfigurable gate array |
| 04/05/2001 | WO2001024367A1 Noise tolerant conductance-based logic gate and methods of operation and manufacturing thereof |
| 04/05/2001 | WO2001024066A1 A regionally time multiplexed emulation system |
| 04/05/2001 | WO2001023901A1 A reconfigurable integrated circuit with integrated debugging facilities for use in an emulation system |
| 04/05/2001 | US20010000133 Semiconductor integrated circuit device and method of activating the same |
| 04/05/2001 | DE10047451A1 Data output circuit for semiconductor component, has output driver unit to pass output driver event in response to output of level shifter circuit after maintaining data output connection in high impedance state |
| 04/04/2001 | EP1089433A1 A method and apparatus for level shifting |
| 04/04/2001 | EP1088276A1 Interface module with protection circuit and method of protecting an interface |
| 04/03/2001 | US6212670 Method for implementing a programmable logic device having look-up table and product-term circuitry |
| 04/03/2001 | US6212591 Configurable I/O circuitry defining virtual ports |
| 04/03/2001 | US6212586 Hot-swappable high speed point-to-point interface |
| 04/03/2001 | US6212402 System connector |
| 04/03/2001 | US6212050 Circuit and method for protecting input/output stage of a low voltage integrated circuit device from a failure of the internal power supply or in the power-up sequencing of power supplies |
| 04/03/2001 | US6211725 Low powder CMOS circuit |
| 04/03/2001 | US6211720 Logic circuit |
| 04/03/2001 | US6211715 Semiconductor integrated circuit incorporating therein clock supply circuit |
| 04/03/2001 | US6211714 System for Distributing Clocks |
| 04/03/2001 | US6211707 Output buffer circuit with preset function |
| 04/03/2001 | US6211704 Asynchronous sensing differential logic (ASDL) circuit |
| 04/03/2001 | US6211702 Input circuit |
| 04/03/2001 | US6211701 Low power line switching circuit, device and method |
| 04/03/2001 | US6211700 Data transfer device with a post charge logic |
| 04/03/2001 | US6211699 High performance CML to CMOS converter |
| 04/03/2001 | US6211696 Hybrid product term and look-up table-based programmable logic device with improved speed and area efficiency |
| 04/03/2001 | US6211695 FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections |
| 04/03/2001 | US6211694 Bus driver having noise removing circuit |
| 04/03/2001 | US6211693 Testability circuit for cascode circuits used for high voltage interface |
| 04/03/2001 | US6211660 MOS transistor output circuits using PMOS transistors |
| 04/03/2001 | US6211456 Method and apparatus for routing 1 of 4 signals |
| 03/29/2001 | WO2001022591A1 Two-stage muller c-element |
| 03/29/2001 | WO2001022590A1 Reconfigurable programmable sum of products generator |
| 03/29/2001 | WO2001022589A1 Configuration state memory for functional blocks on a reconfigurable chip |
| 03/29/2001 | WO2001022585A1 Adaptive dead time control for pushing-pull switching circuits |
| 03/29/2001 | DE19944248A1 Inputbuffer einer integrierten Halbleiterschaltung Input buffer of a semiconductor integrated circuit |
| 03/28/2001 | EP1087529A2 Latching domino logic circuit with hold time |
| 03/28/2001 | EP1087528A1 Output circuit for semiconductor integrated circuit |
| 03/28/2001 | EP1086531A1 Logic gate |
| 03/28/2001 | CN1289445A Fuse circuit having zero power draw for partially blown condition |
| 03/28/2001 | CN1289126A Semiconductor apparatus |
| 03/27/2001 | US6208907 Domino to static circuit technique |
| 03/27/2001 | US6208685 Matched filter |
| 03/27/2001 | US6208282 A/D converter with input capacitor, feedback capacitor, and two invertors |
| 03/27/2001 | US6208200 Level shift circuit with low voltage operation |
| 03/27/2001 | US6208178 CMOS over voltage-tolerant output buffer without transmission gate |
| 03/27/2001 | US6208177 Output buffer having immediate onset of gentle state transition |
| 03/27/2001 | US6208171 Semiconductor integrated circuit device with low power consumption and simple manufacturing steps |
| 03/27/2001 | US6208170 Semiconductor integrated circuit having a sleep mode with low power and small area |
| 03/27/2001 | US6208168 Output driver circuits having programmable pull-up and pull-down capability for driving variable loads |
| 03/27/2001 | US6208167 Voltage tolerant buffer |
| 03/27/2001 | US6208166 Circuit and method for implementing combinatorial logic functions |
| 03/27/2001 | US6208163 FPGA configurable logic block with multi-purpose logic/memory circuit |
| 03/27/2001 | US6208162 Technique for preconditioning I/Os during reconfiguration |
| 03/27/2001 | US6208161 Differential signal transmission circuit |
| 03/22/2001 | WO2001020784A1 Multi-clock integrated circuit with clock generator and bi-directional clock pin arrangement |
| 03/22/2001 | WO2001020783A1 Method and apparatus for reducing peak power consumption |
| 03/22/2001 | WO2001020782A1 Circuit arrangement for controlling a load |
| 03/22/2001 | DE19944519A1 Schaltungsanordnung zum Ansteuern einer Last Circuit arrangement for driving a load |
| 03/22/2001 | DE19938890A1 Integrierter Schaltkreis und Schaltungsanordnung zur Stromversorgung eines integrierten Schaltkreises The integrated circuit and the circuit arrangement for the power supply of an integrated circuit |
| 03/22/2001 | DE10017070A1 Buffer circuit for semiconductor memory has control signal generator which produces control signal based on output signals of two pull=down switch circuits that individually turn into respective states |
| 03/21/2001 | EP1085656A2 Dynamic logic circuitry using quantum mechanical tunneling structures |
| 03/21/2001 | EP1085575A1 Electronic device for controlling the "bouncing" in electronic circuits integrated on semiconductor substrate |
| 03/21/2001 | EP0570597B1 Flash memory improved in erasing characteristic, and circuit therefor |
| 03/21/2001 | CN1288290A Input buffer for semiconductor integrated circuit |
| 03/20/2001 | US6205077 One-time programmable logic cell |