Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
11/2000
11/28/2000US6154057 Bi-directional voltage translator
11/28/2000US6154055 Programmable logic array integrated circuit devices
11/28/2000US6154053 Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch
11/28/2000US6154052 Combined tristate/carry logic mechanism
11/28/2000US6154051 Tileable and compact layout for super variable grain blocks within FPGA device
11/28/2000US6154050 Internal tristate bus with arbitration logic
11/28/2000US6154049 Multiplier fabric for use in field programmable gate arrays
11/28/2000US6154048 Structure and method for loading narrow frames of data from a wide input bus
11/28/2000US6154047 Bus configuration and input/output buffer
11/28/2000US6154046 Preconditioning input signals of logic gates for glitch-free output signal
11/28/2000US6154045 Method and apparatus for reducing signal transmission delay using skewed gates
11/28/2000US6154044 Superconductive logic gate and random access memory
11/28/2000US6153914 Output circuit for integrated circuits
11/23/2000WO2000070765A1 Cascode signal driver with low harmonic content
11/23/2000WO2000070761A1 Circuit arrangement for generating current impulses in the supply current of integrated circuits
11/23/2000WO2000069245A2 Output buffer with independently controllable current mirror legs
11/23/2000WO2000044095A3 Fpga integrated circuit having embedded sram memory blocks and interconnect channel for broadcasting address and control signals
11/23/2000WO2000019608A3 Circuit for processing data signals
11/23/2000DE19950543C1 Integrated circuit arrangement with transistors working voltage control e.g. for differential amplifier
11/23/2000DE19920721A1 Programming circuit for electrically-programmable element
11/23/2000DE10024690A1 Input buffer circuit especially for semiconductor component, has differential input for receiving input signal and reference clock, with current supply and output buffering
11/23/2000CA2372183A1 Output buffer with independently controllable current mirror legs
11/22/2000EP1053616A1 Damping circuit for two-wire bus system
11/22/2000EP0846289A4 Field programmable gate array with distributed ram and increased cell utilization
11/21/2000US6151686 Managing an information retrieval problem
11/21/2000US6151648 High speed bus system and method for using voltage and timing oscillating references for signal detection
11/21/2000US6151258 Programmable logic device with multi-port memory
11/21/2000US6151257 Apparatus for receiving/transmitting signals in an input/output pad buffer cell
11/21/2000US6151199 Semiconductor integrated circuit device
11/21/2000US6150870 Adjustable substrate voltage applying circuit of a semiconductor device
11/21/2000US6150869 Method and apparatus for body control in silicon-on-insulator (SOI) domino circuits
11/21/2000US6150848 Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication
11/21/2000US6150844 High voltage tolerance output stage
11/21/2000US6150843 Five volt tolerant I/O buffer
11/21/2000US6150842 Variable grain architecture for FPGA integrated circuits
11/21/2000US6150841 Enhanced macrocell module for high density CPLD architectures
11/21/2000US6150839 Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
11/21/2000US6150838 FPGA configurable logic block with multi-purpose logic/memory circuit
11/21/2000US6150837 Enhanced field programmable gate array
11/21/2000US6150836 Multilevel logic field programmable device
11/21/2000US6150835 Method and apparatus for fast production programming and low-voltage in-system writes for programmable logic device
11/21/2000US6150834 Elimination of SOI parasitic bipolar effect
11/21/2000US6150699 Tri-voltage Bi-CMOS semiconductor device
11/21/2000US6149319 Computer system host adapter for controlling signal levels to peripheral cards
11/16/2000WO2000069073A1 Heterogeneous programmable gate array
11/16/2000WO2000069072A1 Apparatus and methods for dynamically defining variably sized autonomous sub-arrays within a programmable gate array
11/16/2000WO2000069071A1 Complementary current mode driver
11/16/2000WO2000069070A1 Circuit arrangement and optical read/write device including the circuit arrangement
11/16/2000WO2000068775A1 Apparatus and method for programmable datapath arithmetic arrays
11/16/2000DE19933800C1 Semiconductor integrated circuit
11/16/2000CA2372364A1 Apparatus and method for programmable datapath arithmetic arrays
11/16/2000CA2371080A1 Heterogeneous programmable gate array
11/16/2000CA2371077A1 Apparatus and methods for dynamically defining variably sized autonomous sub-arrays within a programmable gate array
11/15/2000EP1052778A1 Method and device for logically combining signals using magnetic means
11/15/2000EP1051803A1 Slew rate control circuit
11/15/2000EP0980546A4 Non-intrusive power control for computer systems
11/15/2000EP0819340A4 Logic cell and routing architecture in a field programmable gate array
11/15/2000CN1273459A Output through rate-of-change control circuit
11/15/2000CN1273437A CMOS semiconductor integral circuit
11/14/2000USRE36952 One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture
11/14/2000US6147890 FPGA with embedded content-addressable memory
11/14/2000US6147884 Method and apparatus for low-power charge transition in an I/O system of an integrated circuit
11/14/2000US6147540 High voltage input buffer made by a low voltage process and having a self-adjusting trigger point
11/14/2000US6147539 Method and structure for improving power consumption on a component while maintaining high operating frequency
11/14/2000US6147520 Integrated circuit having controlled impedance
11/14/2000US6147513 Method and circuit for logic input buffer
11/14/2000US6147511 Overvoltage-tolerant interface for integrated circuits
11/14/2000US6147510 Integrated circuit for handling buffer contention and method thereof
11/14/2000US6147509 Semiconductor logical device capable of circuit switching without being influenced by transitional effects
11/14/2000US6147508 Power consumption control mechanism and method therefor
11/09/2000WO2000067380A1 Integrated circuit low leakage power circuitry for use with an advanced cmos process
11/09/2000WO2000067378A1 Method and apparatus for a single event upset (seu) tolerant clock splitter
11/09/2000WO2000067377A2 Mask configurable smart power circuits - applications and gs-nmos devices
11/09/2000WO2000055971A8 Methods and apparatus for bipolar elimination in silicon-on-insulator (soi) domino circuits
11/09/2000WO2000041181A3 Seu hardening circuit
11/09/2000CA2336107A1 Mask configurable smart power circuits - applications and gs-nmos devices
11/08/2000EP1050968A1 CMOS semiconductor integrated circuit
11/08/2000EP1050106A1 Reverse current throttling of a mos transistor
11/08/2000EP0830735B1 Field programmable gate array (fpga) with interconnect encoding
11/07/2000US6144257 Bus control buffer amplifier
11/07/2000US6144251 Semiconductor integrated circuit device having component circuits free from through-current in transition period between active mode and sleep mode
11/07/2000US6144240 Low noise buffer circuit for increasing digital signal transition slew rates
11/07/2000US6144227 MOS logic circuit and semiconductor apparatus including the same
11/07/2000US6144225 Programmable integrated circuit having metal plate capacitors that provide local switching energy
11/07/2000US6144223 Integrated circuit SCSI input receiver having precision high speed input buffer with hysteresis
11/07/2000US6144221 Voltage tolerant interface circuit
11/07/2000US6144220 FPGA Architecture using multiplexers that incorporate a logic gate
11/07/2000US6144218 High speed analog compensated input buffer
11/07/2000US6144217 Low switching noise logic circuit
11/02/2000WO2000065788A1 Self-compensating output buffer
11/02/2000WO2000065428A1 A method and apparatus to power up an integrated device from a low power state
11/02/2000EP1048109A1 Current control technique
11/02/2000EP0809884B1 Sense amplifier with pull-up circuit for accelerated latching of logic level output data
11/02/2000DE10015260A1 Reversible adiabatic logical circuit for implementing logical forward function has compensation reduction in the oscillation to be attributed to a threshold voltage value
10/2000
10/31/2000US6141770 Fault tolerant computer system
10/31/2000US6141766 System and method for providing synchronous clock signals in a computer
10/31/2000US6141761 Low power consuming operating device for digital signal processing using a probability distribution of input digital signals and predetermined output signals
10/31/2000US6141258 Programmable impedance output buffer drivers, semiconductor devices and static random access memories provided with a progammable impedance output port
10/31/2000US6141200 Stacked PFET off-chip driver with a latch bias generator for overvoltage protection
10/31/2000US6140865 Semiconductor integrated circuit device with a stable operating internal circuit
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