| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 06/28/2001 | US20010005160 Reference voltage generation circuit using source followers |
| 06/28/2001 | US20010005153 Semiconductor integrated circuit |
| 06/28/2001 | US20010005148 Semiconductor intergrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout |
| 06/28/2001 | US20010005147 Semiconductor circuit including output buffer circuit and drive circuit for driving output buffer circuit |
| 06/28/2001 | CA2829416A1 Solution processed devices |
| 06/27/2001 | EP1111791A1 Logic circuit and full adder using the same |
| 06/27/2001 | EP1111790A1 Dynamic impedance compensation circuit and method |
| 06/27/2001 | EP1111782A2 Differential sense amplifier circuit and dynamic logic circuit using the same |
| 06/27/2001 | EP1111615A1 Logic circuit |
| 06/27/2001 | EP1110323A1 Fast reconfigurable programmable device |
| 06/27/2001 | EP1110322A1 Electronic circuit |
| 06/27/2001 | EP1110321A1 Method and circuitry for high speed buffering of clock signals |
| 06/27/2001 | EP1110320A1 Output driving circuit |
| 06/27/2001 | EP1110319A1 Dc output level compensation circuit |
| 06/27/2001 | CN1301430A Circuit for reducing leaking current |
| 06/27/2001 | CN1301024A Differential reading-out amplifying circuit and dynamic logic circuit for using it |
| 06/27/2001 | CN1301023A Logic circuit |
| 06/26/2001 | US6253263 System with logic gates having a progressive number of inputs connected to a first connection matrix receiving signals to be arbitrated from peripheral devices |
| 06/26/2001 | US6252792 Field programmable processor arrays |
| 06/26/2001 | US6252452 Semiconductor device |
| 06/26/2001 | US6252448 Coincident complementary clock generator for logic circuits |
| 06/26/2001 | US6252432 Differential-input/single-ended-output translator |
| 06/26/2001 | US6252426 High speed logic family |
| 06/26/2001 | US6252425 Method and apparatus for an N-NARY logic circuit |
| 06/26/2001 | US6252423 Voltage tolerant interface circuit |
| 06/26/2001 | US6252422 Overvoltage-tolerant interface for intergrated circuits |
| 06/26/2001 | US6252421 Differential, high speed, ECL to CMOS converter |
| 06/26/2001 | US6252418 Reduced area active above-supply and below-ground noise suppression circuits |
| 06/26/2001 | CA2205893C Coupling arrangement in a terminating circuit |
| 06/21/2001 | WO2001045336A1 An arrangement for reducing power dissipation in a line driver |
| 06/21/2001 | WO2001045260A1 Electronic component with reduced inductive coupling |
| 06/21/2001 | WO2001045258A2 Method for implementing a physical design for a dynamically reconfigurable logic circuit |
| 06/21/2001 | WO2001044913A1 Interface device and information processing system |
| 06/21/2001 | US20010004748 Bus system |
| 06/21/2001 | US20010004387 Arrangement for reducing power dissipation in a line driver |
| 06/21/2001 | US20010004218 Semiconductor integrated circuit device having power reduction mechanism |
| 06/21/2001 | US20010004217 Signal transmission circuit on semiconductor integrated circuit chip |
| 06/21/2001 | CA2393971A1 Method for implementing a physical design for a dynamically reconfigurable logic circuit |
| 06/19/2001 | US6249462 Data output circuit that can drive output data speedily and semiconductor memory device including such a data output circuit |
| 06/19/2001 | US6249453 Voltage controlled spintronic devices for logic applications |
| 06/19/2001 | US6249279 Data line drive device |
| 06/19/2001 | US6249171 Method and apparatus for galvanically isolating two integrated circuits from each other |
| 06/19/2001 | US6249169 Transistor output circuit |
| 06/19/2001 | US6249151 Inverter for outputting high voltage |
| 06/19/2001 | US6249148 Low power variable base drive circuit |
| 06/19/2001 | US6249147 Method and apparatus for high speed on-chip signal propagation |
| 06/19/2001 | US6249146 MOS output buffer with overvoltage protection circuitry |
| 06/19/2001 | US6249145 Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit |
| 06/19/2001 | US6249144 Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources |
| 06/19/2001 | US6249143 Programmable logic array integrated circuit with distributed random access memory array |
| 06/19/2001 | US6249134 Semiconductor integrated circuit device and testing method thereof |
| 06/14/2001 | WO2001043287A1 Method and apparatus for an n-nary logic circuit |
| 06/14/2001 | WO2001043135A1 A prefetch write driver for a random access memory |
| 06/14/2001 | WO2001042054A1 Circuit for activating a can (car area network) bus control unit |
| 06/14/2001 | WO2000054410A8 Logic circuit protected against transitory perturbations |
| 06/14/2001 | US20010003844 Techniques for programming programmable logic array devices |
| 06/14/2001 | US20010003511 Voltage-level shifter and semiconductor memory using the same |
| 06/14/2001 | US20010003429 Logical circuit |
| 06/14/2001 | US20010003428 Semiconductor device |
| 06/13/2001 | EP1107642A2 Condenser microphone |
| 06/13/2001 | EP1105968A1 Current-controlled output buffer |
| 06/13/2001 | EP1078462A4 Global signal distribution architecture in a field programmable gate array |
| 06/13/2001 | DE19959405A1 Reconfigurable equipment interface has at least one connection associated with several functional equipment units controlled by control circuit so only one unit is connected at any time |
| 06/13/2001 | DE19959402A1 Driver circuit for low Ohmic impedance load compares load logic state level with desired logic state level, automatically switches off associated driver circuit if coincidence inadequate |
| 06/13/2001 | DE10031837C1 Complementary MOSFET bus driver circuit has input and output stages each provided with 2 complementary MOSFET's connected in series with diode between MOSFET's of input stage bridged by MOSFET |
| 06/13/2001 | CN1299228A Capacitor type microphone |
| 06/12/2001 | US6247059 Transaction state broadcast method using a two-stage multicast in a multiple processor cluster |
| 06/12/2001 | US6246625 Semiconductor integrated circuit device having hierarchical power source arrangement |
| 06/12/2001 | US6246266 Dynamic logic circuits using selected transistors connected to absolute voltages and additional selected transistors connected to selectively disabled voltages |
| 06/12/2001 | US6246265 Semiconductor integrated logic circuit with sequential circuits capable of preventing subthreshold leakage current |
| 06/12/2001 | US6246263 MOS output driver, and circuit and method of controlling same |
| 06/12/2001 | US6246262 Output buffer for a low voltage differential signaling receiver |
| 06/12/2001 | US6246260 Programmable logic integrated circuit architecture incorporating a global shareable expander |
| 06/12/2001 | US6246259 High-speed programmable logic architecture having active CMOS device drivers |
| 06/12/2001 | US6246256 Quantized queue length arbiter |
| 06/12/2001 | US6245634 Method for design and manufacture of semiconductors |
| 06/12/2001 | CA2100727C Optimization circuit |
| 06/07/2001 | WO2001041309A1 Programmable device with an embedded portion for receiving a standard circuit design |
| 06/07/2001 | US20010002798 High Voltage Tolerable Input Buffer |
| 06/07/2001 | US20010002797 Logic gate |
| 06/07/2001 | US20010002796 Programmable multi-standard I/O architecture for FPGAs |
| 06/06/2001 | CN1298521A Method for configuring data flow processors and modules with a two-or multidimensional programmable cell structure (FPGAs, DPGAs or similar) without producing deadlocks |
| 06/06/2001 | CN1298520A Method for cacheing configuration data of data flow processors and modules with a two-or multidimensional programmable cell structure (FPGAs DPGAs or similar) according to a hierarchy |
| 06/06/2001 | CN1297836A Equipment and method for cutting spacer bar |
| 06/05/2001 | US6243779 Noise reduction system and method for reducing switching noise in an interface to a large width bus |
| 06/05/2001 | US6243664 Methods for maximizing routability in a programmable interconnect matrix having less than full connectability |
| 06/05/2001 | US6243304 Sample and load scheme for observability internal nodes in a PLD |
| 06/05/2001 | US6242980 Differential amplifier circuit |
| 06/05/2001 | US6242973 Bootstrapped CMOS driver |
| 06/05/2001 | US6242962 Level shift circuit having plural level shift stage stepwise changing potential range without applying large potential difference to component transistors |
| 06/05/2001 | US6242952 Inverting hold time latch circuits, systems, and methods |
| 06/05/2001 | US6242951 Adiabatic charging logic circuit |
| 06/05/2001 | US6242949 Digital voltage translator and its method of operation |
| 06/05/2001 | US6242948 Semiconductor integrated circuit device |
| 06/05/2001 | US6242947 PLD having a window pane architecture with segmented interconnect wiring between logic block arrays |
| 06/05/2001 | US6242946 Embedded memory block with FIFO mode for programmable logic device |
| 06/05/2001 | US6242945 Field programmable gate array with mask programmable I/O drivers |
| 06/05/2001 | US6242944 Real-time reconfigurable vision computing system |
| 06/05/2001 | US6242943 Programmable multi-standard I/O architecture for FPGAS |
| 06/05/2001 | US6242941 Reducing I/O noise when leaving programming mode |