Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
12/2000
12/26/2000US6166985 Integrated circuit low leakage power circuitry for use with an advanced CMOS process
12/26/2000US6166971 Method of and apparatus for correctly transmitting signals at high speed without waveform distortion
12/26/2000US6166969 Method and apparatus for a level shifter for use in a semiconductor memory device
12/26/2000US6166669 Protection from inbound signal noise caused by inductively coupled outbound signal transitions by controlling decision threshold
12/26/2000US6166584 Forward biased MOS circuits
12/26/2000US6166583 Semiconductor device, and operating device, signal converter, and signal processing system using the semiconductor device
12/26/2000US6166582 Method and apparatus of an output buffer for controlling the ground bounce of a semiconductor device
12/26/2000US6166580 CMOS high-to-low voltage buffer
12/26/2000US6166577 Semiconductor integrated circuit device and microcomputer
12/26/2000US6166576 Method and apparatus for controlling timing of digital components
12/26/2000US6166575 Signal transmission circuit achieving significantly improved response time of a driven circuit, CMOS semiconductor device and circuit board therefor
12/26/2000US6166570 Output buffer circuit with switchable common mode output level
12/26/2000US6166564 Control circuit for clock enable staging
12/26/2000US6166563 Method and apparatus for dual mode output buffer impedance compensation
12/26/2000US6166562 Semiconductor integrated circuit device
12/26/2000US6166561 Method and apparatus for protecting off chip driver circuitry employing a split rail power supply
12/26/2000US6166559 Redundancy circuitry for logic circuits
12/23/2000CA2312129A1 High speed level shift circuit for low voltage output
12/21/2000WO2000077977A2 Pass-driver circuit for a two-conductor bus-system
12/21/2000DE19926173A1 Bustreiberschaltung für ein Zweileiter-Bussystem Bus driver circuit for a two-wire bus system
12/20/2000EP1061525A1 Row decoder for a nonvolatile memory with possibility of selectively biasing word lines to positive or negative voltages
12/19/2000US6163499 Programmable impedance output buffer drivers, semiconductor devices and static random access memories provided with a programmable impedance output port
12/19/2000US6163486 Output circuit of semiconductor memory device
12/19/2000US6163197 Low noise method for interconnecting analog and digital integrated circuits
12/19/2000US6163188 Input buffer and input-output buffer in full compliance with IDDQ testability
12/19/2000US6163180 Data output circuit with reduced output noise
12/19/2000US6163179 Voltage level transfer
12/19/2000US6163178 Impedance controlled output driver
12/19/2000US6163177 Semiconductor integrated circuit device having output buffer
12/19/2000US6163174 Digital buffer circuits
12/19/2000US6163173 Method and apparatus for implementing adjustable logic threshold in dynamic circuits for maximizing circuit performance
12/19/2000US6163172 Clock loss detector
12/19/2000US6163171 Pull-up and pull-down circuit
12/19/2000US6163170 Level converter and semiconductor device
12/19/2000US6163169 CMOS tri-state control circuit for a bidirectional I/O with slew rate control
12/19/2000US6163168 Efficient interconnect network for use in FPGA device having variable grain architecture
12/19/2000US6163167 Method for generating an FPGA two turn routing structure with lane changing and minimum diffusion area
12/19/2000US6163166 Programmable logic device with selectable schmitt-triggered and threshold-triggered buffers
12/19/2000US6163165 Method for operating an information handling system
12/14/2000WO2000076072A1 SCALABLE ARCHITECTURE FOR HIGH DENSITY CPLD's HAVING TWO-LEVEL HIERARCHY OF ROUTING RESOURCES
12/14/2000WO2000076068A2 Single rail domino logic for four-phase clocking scheme
12/14/2000WO2000075794A1 Interface for coupling a bus node to the bus line of a bus system
12/14/2000DE19926095A1 Interface zum Ankoppeln eines Busteilnehmers an die Busleitung eines Bussystems Interface for coupling to a bus station to the bus line of a bus system
12/13/2000EP1058967A1 Single output transistor output stage for interface applications
12/13/2000CN1276905A Ferroelectric data processing device
12/12/2000US6160735 Negative voltage level shifter circuit and nonviolatile semiconductor storage device including the circuit
12/12/2000US6160572 Tuner for cable modem
12/12/2000US6160430 Powerup sequence artificial voltage supply circuit
12/12/2000US6160423 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines
12/12/2000US6160422 Power saving clock buffer
12/12/2000US6160421 Voltage translator circuit which allows for variable low voltage signal translation
12/12/2000US6160420 Programmable interconnect architecture
12/12/2000US6160419 Programmable logic architecture incorporating a content addressable embedded array block
12/12/2000US6160418 Integrated circuit with selectively disabled logic blocks
12/12/2000US6160417 Termination circuits and related output buffers
12/12/2000US6160416 Full CMOS slew rate controlled input/output buffer
12/07/2000WO2000074239A1 A level converter provided with slew-rate controlling means
12/07/2000WO2000074069A1 Method and apparatus for testing an impedance-controlled input/output (i/o) buffer in a highly efficient manner
12/06/2000EP1058386A1 Semiconductor integrated circuit device, recording medium stored with cell library, and method for designing semiconductor integrated circuit
12/06/2000EP1058385A2 Comparator and voltage controlled oscillator circuit
12/06/2000EP1058271A1 CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching
12/06/2000EP1057263A1 High speed pin driver integrated circuit architecture for commercial automatic test equipment applications
12/06/2000EP1057262A1 Overvoltage-protected i/o buffer
12/06/2000EP1057255A1 Method and circuitry for the transmission of signals
12/06/2000EP1057117A2 METHOD FOR CACHEING CONFIGURATION DATA OF DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) ACCORDING TO A HIERARCHY
12/06/2000EP1057102A2 METHOD FOR CONFIGURING DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) WITHOUT PRODUCING DEADLOCKS
12/05/2000US6157240 Output logic setting circuit in semiconductor integrated circuit
12/05/2000US6157236 Parametric tuning of an integrated circuit after fabrication
12/05/2000US6157231 Delay stabilization system for an integrated circuit
12/05/2000US6157225 Driving circuit with three output levels, one output level being a boosted level
12/05/2000US6157224 High speed pin driver integrated circuit architecture for commercial automatic test equipment applications
12/05/2000US6157222 Low power adjustable input threshold circuit
12/05/2000US6157216 Circuit driver on SOI for merged logic and memory circuits
12/05/2000US6157215 Method and apparatus for controlling impedance
12/05/2000US6157214 Wiring of cells in logic arrays
12/05/2000US6157212 Programmable logic device with expandable-width memory regions
12/05/2000US6157211 FPGA using RAM control signal lines as routing or logic resources after configuration
12/05/2000US6157209 Loadable up-down counter with asynchronous reset
12/05/2000US6157208 Programmable logic device macrocell with improved logic capability
12/05/2000US6157205 Grounding scheme for a high-speed data channel
12/05/2000US6157203 Input circuit with improved operating margin using a single input differential circuit
12/05/2000US6157051 Multiple function array based application specific integrated circuit
11/2000
11/30/2000WO2000036749A9 Methods for configuring fpga's for providing symmetric routing to differently-directed interconnect resources
11/30/2000DE10023976A1 Switching network for use with cross coupled switches, has exclusive OR logic for changeover
11/29/2000CN1274997A High-speed input buffer circuit for low-voltage interface
11/29/2000CN1274990A Input buffer circuit
11/29/2000CN1059059C Method of weak pull-up disable and mechanism therefor for use with microcontroller in integrated circuit
11/28/2000US6154397 Semiconductor memory device having stabilization circuit for stable signal transmission
11/28/2000US6154394 Data input-output circuit and semiconductor data storage device provided therewith
11/28/2000US6154120 Method and apparatus for an N-nary equality comparator
11/28/2000US6154089 Fast bus driver with reduced standby power consumption
11/28/2000US6154084 Method for switching voltages higher than a supply voltage on a semiconductor chip with a circuit configuration
11/28/2000US6154083 Ground bounce control using DLL to optimize output stage di/dt using output driver replica
11/28/2000US6154070 Control circuit and semiconductor integrated circuit device
11/28/2000US6154069 Circuit for driving capacitive load
11/28/2000US6154066 Apparatus and method for interfacing integrated circuits having incompatible I/O signal levels
11/28/2000US6154062 Semiconductor integrated circuits with power reduction mechanism
11/28/2000US6154060 Signaling circuit with substantially constant output impedance
11/28/2000US6154059 High performance output buffer
11/28/2000US6154058 Output buffer
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