| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 02/20/2001 | US6192069 Circuit and methodology for transferring signals between semiconductor devices |
| 02/20/2001 | US6191647 Low noise integrated circuit device for reducing a noise on LSI power supply nets to supply electric charges required to operate IC |
| 02/20/2001 | US6191636 Input buffer/level shifter |
| 02/20/2001 | US6191635 Level shifting circuit having a fixed output common mode level |
| 02/20/2001 | US6191628 Circuit for controlling the slew rate of a digital signal |
| 02/20/2001 | US6191626 Method and apparatus for compensating input threshold variations on input buffers |
| 02/20/2001 | US6191619 Translators and methods for converting differential signals to single-ended signals |
| 02/20/2001 | US6191618 Contention-free, low clock load domino circuit topology |
| 02/20/2001 | US6191617 Input buffer |
| 02/20/2001 | US6191615 Logic circuit having reduced power consumption |
| 02/20/2001 | US6191613 Programmable logic device with delay-locked loop |
| 02/20/2001 | US6191612 Enhanced I/O control flexibility for generating control signals |
| 02/20/2001 | US6191611 Driver circuitry for programmable logic devices with hierarchical interconnection resources |
| 02/20/2001 | US6191610 Method for implementing large multiplexers with FPGA lookup tables |
| 02/20/2001 | US6191609 Combination of global clock and localized clocks |
| 02/20/2001 | US6191608 Techniques for programming programmable logic array devices |
| 02/20/2001 | US6191606 Method and apparatus for reducing standby leakage current using input vector activation |
| 02/20/2001 | US6191573 Ringing preventive circuit, device under test board, pin electronics card, and semiconductor device |
| 02/15/2001 | WO2001011778A1 Circuit configuration for supplying power to an integrated circuit via a pad |
| 02/15/2001 | WO2001011777A1 An integrated circuit provided with a fail-safe mode |
| 02/15/2001 | WO2001011750A1 Circuits for dynamic turn off of nmos output drivers during eos/esd stress |
| 02/15/2001 | WO2001011685A1 Double triggering mechanism for achieving faster turn-on |
| 02/14/2001 | EP0723705B1 Method for combining a plurality of independently operating circuits within a single package |
| 02/14/2001 | EP0717890B1 High voltage swing interface stage |
| 02/14/2001 | CN2419745Y Logic signal shaping device without external power supply |
| 02/14/2001 | CN1283853A Semiconductor memory for reducing current loss when keeping data mode |
| 02/13/2001 | US6188273 Integrated circuit having a contact-making point for selecting an operating mode of the integrated circuit |
| 02/13/2001 | US6188263 Electrostatic protection circuit |
| 02/13/2001 | US6188254 Data output buffer with high drivability in semiconductor device |
| 02/13/2001 | US6188248 Output synchronization-free, high-fanin dynamic NOR gate |
| 02/13/2001 | US6188247 Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements |
| 02/13/2001 | US6188246 Semiconductor circuit with sequential circuit which can prevent leakage current |
| 02/13/2001 | US6188245 Bus circuit which prevents current from flowing from a power supply of one circuit to a power supply of another circuit for a predetermined period |
| 02/13/2001 | US6188244 Hysteresis input buffer |
| 02/13/2001 | US6188243 Input/output circuit with high input/output voltage tolerance |
| 02/13/2001 | US6188242 Virtual programmable device and method of programming |
| 02/13/2001 | US6188240 Programmable function block |
| 02/13/2001 | US6188238 Method for operating an information handling system |
| 02/13/2001 | US6188237 Impedance matching circuit, high speed semiconductor integrated circuit employing the same and computer system employing the integrated circuit |
| 02/13/2001 | US6188236 Arrangement and method relating to digital information in superconducting circuits |
| 02/13/2001 | US6188091 FPGA one turn routing structure using minimum diffusion area |
| 02/11/2001 | CA2311420A1 Method and system for programming fpgas on pc cards without additional hardware |
| 02/08/2001 | WO2000069245A3 Output buffer with independently controllable current mirror legs |
| 02/08/2001 | DE19929231A1 Schaltungsanordnung und Verfahren zur galvanisch getrennten Breitband-Übertragung Circuit arrangement and method for electrically isolated broadband transmission |
| 02/08/2001 | DE10035136A1 Integrated semiconducting circuit has selector of inverted or non-inverted signal depending on readout masking signal, two flip-flop circuits, Exclusive-OR circuit combining flip-flop outputs |
| 02/08/2001 | DE10022770A1 Integrated circuit current read-amplifier design, has output voltage level control circuit provided with first and second resistors and NMOS transistor connected to their point |
| 02/07/2001 | EP1074993A1 Semiconductor memory device with reduced current consumption in data hold mode |
| 02/07/2001 | EP0864203A4 High voltage level shifting cmos buffer |
| 02/07/2001 | CN1283329A High speed ratioed CMOS Logic structure for pulsed input |
| 02/07/2001 | CN1061802C Temp. compensation piezoelectric oscillator |
| 02/06/2001 | USRE37048 Field programmable digital signal processing array integrated circuit |
| 02/06/2001 | US6185126 Self-initializing RAM-based programmable device |
| 02/06/2001 | US6184738 Input buffer for supplying semiconductor device with internal signal based on comparison of external signal with reference potential |
| 02/06/2001 | US6184737 Signal transmission with reduced ringing of signals |
| 02/06/2001 | US6184733 Clock synchronizing circuit |
| 02/06/2001 | US6184730 CMOS output buffer with negative feedback dynamic-drive control and dual P,N active-termination transmission gates |
| 02/06/2001 | US6184728 Output circuit |
| 02/06/2001 | US6184718 Dynamic logic circuit |
| 02/06/2001 | US6184717 Digital signal transmitter and receiver using source based reference logic levels |
| 02/06/2001 | US6184716 High voltage output stage for driving an electric load |
| 02/06/2001 | US6184715 Bus-hold input circuit adapted for receiving input signals with voltage levels higher than the voltage supply thereof |
| 02/06/2001 | US6184713 Scalable architecture for high density CPLDS having two-level hierarchy of routing resources |
| 02/06/2001 | US6184712 FPGA configurable logic block with multi-purpose logic/memory circuit |
| 02/06/2001 | US6184711 Low impact signal buffering in integrated circuits |
| 02/06/2001 | US6184710 Programmable logic array devices with enhanced interconnectivity between adjacent logic regions |
| 02/06/2001 | US6184709 Programmable logic device having a composable memory array overlaying a CLB array |
| 02/06/2001 | US6184708 Method for selecting slew rate for a programmable device |
| 02/06/2001 | US6184707 Look-up table based logic element with complete permutability of the inputs to the secondary signals |
| 02/06/2001 | US6184706 Logic device architecture and method of operation |
| 02/06/2001 | US6184705 Techniques for programming programmable logic array devices |
| 02/06/2001 | US6184704 Design method for compensation of process variation in CMOS digital input circuits |
| 02/06/2001 | US6184703 Method and circuit for reducing output ground and power bounce noise |
| 02/06/2001 | US6184701 Integrated circuit devices having metastability protection circuits therein |
| 02/06/2001 | US6184700 Fail safe buffer capable of operating with a mixed voltage core |
| 02/01/2001 | WO2001008411A1 Field programmable gate array with program encryption |
| 02/01/2001 | WO2001008214A1 Integrated circuit |
| 02/01/2001 | DE19949144C1 Digital driver circuit for IC device has input stages, delay stage, intermediate stage and output stage provided by chain of CMOS-inverters |
| 01/31/2001 | EP1072096A1 Externally supplied interface adapter |
| 01/31/2001 | EP0669055B1 Programmable logic networks |
| 01/31/2001 | CN2417079Y Self check, radio and remote control type theft prevention means for automobile |
| 01/30/2001 | US6182256 Scan flip-flop that simultaneously holds logic values from a serial load and a subsequent parallel load |
| 01/30/2001 | US6181922 Attenuator unit, step attenuator, and electronic apparatus |
| 01/30/2001 | US6181610 Semiconductor device having current auxiliary circuit for output circuit |
| 01/30/2001 | US6181596 Method and apparatus for a RAM circuit having N-Nary output interface |
| 01/30/2001 | US6181542 Method of making a stack-polysilicon capacitor-coupled dual power supply input/output protection circuit |
| 01/30/2001 | US6181193 Using thick-oxide CMOS devices to interface high voltage integrated circuits |
| 01/30/2001 | US6181189 Interface circuit switching between a source-input mode and a sink-input mode |
| 01/30/2001 | US6181182 Circuit and method for a high gain, low input capacitance clock buffer |
| 01/30/2001 | US6181176 Output buffer circuit |
| 01/30/2001 | US6181167 Full duplex CMOS communication |
| 01/30/2001 | US6181166 Tristate driver for integrated circuit interconnects |
| 01/30/2001 | US6181165 Reduced voltage input/reduced voltage output tri-state buffers |
| 01/30/2001 | US6181164 Linear feedback shift register in a programmable gate array |
| 01/30/2001 | US6181163 FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals |
| 01/30/2001 | US6181162 Programmable logic device with highly routable interconnect |
| 01/30/2001 | US6181160 Programmable logic device with hierarchical interconnection resources |
| 01/30/2001 | US6181159 Integrated circuit incorporating a programmable cross-bar switch |
| 01/30/2001 | US6181158 Configuration logic to eliminate signal contention during reconfiguration |
| 01/30/2001 | US6181156 Noise suppression circuits for suppressing noises above and below reference voltages |
| 01/25/2001 | WO2001006658A1 Electronic circuit, especially for a mobile radiotelephone device |