| Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143) |
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| 05/30/2001 | CN1297144A Capacitive pressure transducer |
| 05/30/2001 | CN1066573C Method for mfg. thin-film transistor |
| 05/29/2001 | US6240375 Method of simulating an integrated circuit for error correction in a configuration model, and a computer-readable recording medium |
| 05/29/2001 | US6240021 Nonvolatile semiconductor memory device improved in readout operation |
| 05/29/2001 | US6240012 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield |
| 05/29/2001 | US6239662 Mis variable capacitor and temperature-compensated oscillator using the same |
| 05/29/2001 | US6239649 Switched body SOI (silicon on insulator) circuits and fabrication method therefor |
| 05/29/2001 | US6239638 SR flip flop |
| 05/29/2001 | US6239500 Semiconductor device with common bit contact area |
| 05/29/2001 | US6239490 P-contact for a Group III-nitride semiconductor device and method of making same |
| 05/29/2001 | US6239478 Semiconductor structure for a MOS transistor |
| 05/29/2001 | US6239475 Vertical bipolar transistor having a field shield between the metallic interconnecting layer and the insulation oxide |
| 05/29/2001 | US6239473 Trench isolation for micromechanical devices |
| 05/29/2001 | US6239472 MOSFET structure having improved source/drain junction performance |
| 05/29/2001 | US6239471 MIS transistor and manufacturing method thereof |
| 05/29/2001 | US6239470 Active matrix electro-luminescent display thin film transistor |
| 05/29/2001 | US6239468 Sensor thin film transistor for an optical detecting sensor |
| 05/29/2001 | US6239466 Insulated gate bipolar transistor for zero-voltage switching |
| 05/29/2001 | US6239465 Non-volatile semiconductor memory device having vertical transistors with the floating and control gates in a trench and fabrication method therefor |
| 05/29/2001 | US6239464 Semiconductor gate trench with covered open ends |
| 05/29/2001 | US6239463 Low resistance power MOSFET or other device containing silicon-germanium layer |
| 05/29/2001 | US6239461 Semiconductor device capacitor having a recessed contact plug |
| 05/29/2001 | US6239452 Self-aligned silicide gate technology for advanced deep submicron MOS device |
| 05/29/2001 | US6239450 Negative differential resistance device based on tunneling through microclusters, and method therefor |
| 05/29/2001 | US6239449 Quantum dot infrared photodetectors (QDIP) |
| 05/29/2001 | US6239042 Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devices |
| 05/29/2001 | US6239041 Method for fabricating semiconductor integrated circuit device |
| 05/29/2001 | US6239037 Autoaligned etching process for realizing word lines and improving the reliability of semiconductor integrated memory devices |
| 05/29/2001 | US6239033 Making a device using nitride iii-v compound semiconductors on one major surface of a single-crystal substrate; thinning said single-crystal substrate by processing the other major surface |
| 05/29/2001 | US6239009 Flash memory device and method for manufacturing the same |
| 05/29/2001 | US6239005 A platinum layer is epitaxially grown in a crystal orientation of by sputtering; after annealing at 600-900 degrees c., a buffer layer made of gallium nitride is epitaxially grown on the platinum layer |
| 05/29/2001 | US6238991 Fabrication process of semiconductor device having an epitaxial substrate |
| 05/29/2001 | US6238989 Process of forming self-aligned silicide on source/drain region |
| 05/29/2001 | US6238988 Method of forming a MOS transistor |
| 05/29/2001 | US6238987 Method to reduce parasitic capacitance |
| 05/29/2001 | US6238985 Semiconductor device and method for fabricating the same |
| 05/29/2001 | US6238982 Multiple threshold voltage semiconductor device fabrication technology |
| 05/29/2001 | US6238981 Process for forming MOS-gated devices having self-aligned trenches |
| 05/29/2001 | US6238980 Method for manufacturing silicon carbide MOS semiconductor device including utilizing difference in mask edges in implanting |
| 05/29/2001 | US6238978 Use of etch to blunt gate corners |
| 05/29/2001 | US6238975 Method for improving electrostatic discharge (ESD) robustness |
| 05/29/2001 | US6238960 Fast MOSFET with low-doped source/drain |
| 05/29/2001 | US6238959 Method of fabricating LDMOS transistor |
| 05/29/2001 | US6238958 Method for forming a transistor with reduced source/drain series resistance |
| 05/29/2001 | US6238957 Forming sacrificial fluorine containing layer on polycrystalline thin film layer by chemical vapor deposition using wf6 and sih4; forming si--f bonds within the thin film layer; removing the sacrificial layer |
| 05/29/2001 | US6238956 Method for manufacturing thin film transistor by using a self-align technology |
| 05/29/2001 | US6238737 Method for protecting refractory metal thin film requiring high temperature processing in an oxidizing atmosphere and structure formed thereby |
| 05/29/2001 | US6238624 A self-addressable, self-assembling microelectronic device is designed and fabricated to actively carry out and control multi-step and multiplex molecular biological reactions in microscopic formats. |
| 05/25/2001 | WO2001037349A1 Vertical heterojunction bipolar transistor |
| 05/25/2001 | WO2001037348A1 Type ii interband heterostructure backward diodes |
| 05/25/2001 | WO2001037347A1 Non-volatile semiconductor memory location and method for producing the same |
| 05/25/2001 | WO2001037346A1 Lateral thin-film soi device having a lateral drift region and method of making such a device |
| 05/25/2001 | WO2001037345A1 Radiation resistant integrated circuit design |
| 05/25/2001 | WO2001037343A1 Circuit configuration for protecting semi-conductor circuits against polarity reversal |
| 05/25/2001 | WO2001037342A2 Dram cell structure with tunnel barrier |
| 05/25/2001 | WO2001037331A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING SiGe HBTs |
| 05/25/2001 | WO2001037330A1 Method for stabilizing oxide-semiconductor interface by using group 5 element and stabilized semiconductor |
| 05/25/2001 | WO2001037328A1 Method for treating a surface of an sic semiconductor layer and schottky contact |
| 05/25/2001 | WO2001037327A1 Pendeoepitaxial growth of gallium nitride layers on sapphire substrates |
| 05/25/2001 | WO2001022475A3 Method for dicing mesa-diodes |
| 05/24/2001 | US20010001724 First strip of metallic conductive material of given stress, overlying a narrower strip of a second conductive material of lower stress; destructive interference between layers lowers edge stress in underlying structures; integrated circuits |
| 05/24/2001 | US20010001721 Masking polysilicon (PS) layer of transistors of the read only memory (ROM) cell, doping the ROM cells in the active areas of the exposed transistors, demasking the PS layer and implanting a second dopant in previously covered layer |
| 05/24/2001 | US20010001550 Integral stress isolation apparatus and technique for semiconductor devices |
| 05/24/2001 | US20010001501 Methods of forming integrated circuit capacitors having doped HSG electrodes and capacitors formed thereby |
| 05/24/2001 | US20010001498 Field effect transistors, integrated circuitry, methods of forming field effect transistor gates, and methods of forming integrated circuitry |
| 05/24/2001 | US20010001497 Semiconductor device and method for manufacturing the same |
| 05/24/2001 | US20010001496 Semiconductor devices |
| 05/24/2001 | US20010001494 Power trench mos-gated device and process for forming same |
| 05/24/2001 | US20010001491 Semiconductor memory device having memory cells each having a conductive body of booster plate and a method for manufacturing the same |
| 05/24/2001 | US20010001488 Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced encapsulation layer |
| 05/24/2001 | US20010001487 Charge transfer device, and driving method and manufacturing method for the same |
| 05/24/2001 | US20010001486 Dual gate fet and process |
| 05/24/2001 | US20010001484 Semiconductor configuration with ohmic contact-connection and method for contact-connecting a semiconductor configuration |
| 05/24/2001 | US20010001483 Dynamic threshold voltage devices with low gate to substrate resistance |
| 05/24/2001 | US20010001482 Process for fabricating thin-film device and thin-film device |
| 05/24/2001 | US20010001385 Boron-doped isotopic diamond and process for producing the same |
| 05/23/2001 | EP1102467A1 Solid-state imaging device, method for driving the same, and image input device |
| 05/23/2001 | EP1102335A2 Thin film transistors |
| 05/23/2001 | EP1102328A1 Integrated capacitor with hybrid dielectric |
| 05/23/2001 | EP1102327A2 Field effect semiconductor device |
| 05/23/2001 | EP1102318A1 Method of forming a diode for integration with a semiconductor device and method of forming a transistor device having an integrated diode |
| 05/23/2001 | EP1102313A2 A top gate self-aligned polysilicon TFT and a method for its production |
| 05/23/2001 | EP1102234A2 Active matrix type display apparatus and drive circuit thereof |
| 05/23/2001 | EP1102111A2 Liquid crystal display device having improved TFTs and a fabrication method thereof |
| 05/23/2001 | EP1101842A2 Substrate for epitaxy of III-V compounds and a method for producing the same |
| 05/23/2001 | EP1101389A2 Method for producing a filled recess in a material layer, integrated circuit produced using said method |
| 05/23/2001 | EP1101087A1 Flexible silicon strain gage |
| 05/23/2001 | DE19955514A1 Schaltungsanordnung zur Verpolsicherung von Halbleiterschaltungen Circuit arrangement for the Polarization of semiconductor circuits |
| 05/23/2001 | DE19953883A1 Anordnung zur Reduzierung des Einschaltwiderstandes von p- oder n-Kanal-Feldeffekttransistoren Arrangement for reduction of the on resistance of p-type or n-channel field-effect transistors |
| 05/23/2001 | DE19953348A1 n-channel MOS-transistor device without latch-up of parasitic bipolar transistor |
| 05/23/2001 | DE10053724A1 MOS-transistor structure with pedestal for protection against electrostatic discharges, has ESD-protection device provided on MOS-transistor base and transistor configuration is generated with an ESD-protection transistor |
| 05/23/2001 | CN1296643A Thin-film transistor, liquid crystal panel, and method for producing the same |
| 05/23/2001 | CN1296639A Method of manufacturing semiconductor device with field effect transistor |
| 05/23/2001 | CN1296630A Voltage boosting circuit including capacitor with reduced parasitic capacitance |
| 05/23/2001 | CN1296293A Complementary double-load field effect transistor and chip system thereof |
| 05/23/2001 | CN1296292A Low power consumption semiconductor power switch device and making method thereof |
| 05/23/2001 | CN1296291A Shape-changed hetrointerface bipolar transistor |
| 05/23/2001 | CN1296290A Linear capacitor structure in CMOS technology |
| 05/23/2001 | CN1296289A Semiconductor device |
| 05/22/2001 | US6236596 Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices |