H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof

Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
12/2002
12/11/2002	EP1264208A2 A method of forming electrodes or pixel electrodes and a liquid crystal display device
12/11/2002	EP0974146B1 Nonvolatile memory
12/11/2002	CN1384974A Solid-source doping for source/drain flash memory
12/11/2002	CN1384973A Trench DMOS transistor having reduced punch through
12/11/2002	CN1384552A Semiconductor device and formation of silicon substrate film
12/11/2002	CN1384549A Semiconductor device and complementary semiconductor device
12/11/2002	CN1384546A 半导体器件 Semiconductor devices
12/11/2002	CN1384543A Flexible integrated monochip circuit
12/11/2002	CN1384536A Manufacture of FET and memory unit in DRAM
12/11/2002	CN1384400A Pattern etching agent of In-Sn oxide and LCD making process
12/11/2002	CN1384394A Liquid crystal display and its making process
12/11/2002	CN1384042A Method of making suspended microstructure
12/11/2002	CN1096115C Semiconductor device fabrication method
12/11/2002	CN1096107C Mos field effect transistor with improved pocket regions for suppressing any short channel effects and method for fabricating the same
12/10/2002	US6493848 Rate equation method and apparatus for simulation of current in a MOS device
12/10/2002	US6493659 Power consumption calculating apparatus and method of the same
12/10/2002	US6493269 Dual cell reading and writing technique
12/10/2002	US6493264 Nonvolatile semiconductor memory, method of reading from and writing to the same and method of manufacturing the same
12/10/2002	US6493199 Vertical zener-triggered SCR structure for ESD protection in integrated circuits
12/10/2002	US6493048 Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same
12/10/2002	US6492712 High quality oxide for use in integrated circuits
12/10/2002	US6492711 Heterojunction bipolar transistor and method for fabricating the same
12/10/2002	US6492700 Thin film transistor liquid crystal display device
12/10/2002	US6492696 Semiconductor device and process of manufacturing the same
12/10/2002	US6492695 Semiconductor arrangement with transistor gate insulator
12/10/2002	US6492694 Highly conductive composite polysilicon gate for CMOS integrated circuits
12/10/2002	US6492693 Low voltage high performance semiconductor devices and methods
12/10/2002	US6492691 High integration density MOS technology power device structure
12/10/2002	US6492690 Semiconductor device having control electrodes with different impurity concentrations
12/10/2002	US6492689 Semiconductor device switching regulator used as a DC regulated power supply
12/10/2002	US6492687 Merged semiconductor device and method
12/10/2002	US6492685 Semiconductor device having a pair of N-channel TFT and P-channel TFT
12/10/2002	US6492684 Silicon-on-insulator chip having an isolation barrier for reliability
12/10/2002	US6492683 Semiconductor device with SOI structure and method of manufacturing the same
12/10/2002	US6492681 Semiconductor device
12/10/2002	US6492680 Semiconductor integrated circuit device
12/10/2002	US6492679 Method for manufacturing a high voltage MOSFET device with reduced on-resistance
12/10/2002	US6492678 High voltage MOS transistor with gate extension
12/10/2002	US6492677 Non-volatile semiconductor memory device and fabrication process thereof
12/10/2002	US6492676 Semiconductor device having gate electrode in which depletion layer can be generated
12/10/2002	US6492674 Semiconductor device having an improved plug structure and method of manufacturing the same
12/10/2002	US6492672 Semiconductor device
12/10/2002	US6492669 Semiconductor device with schottky electrode having high schottky barrier
12/10/2002	US6492665 Semiconductor device
12/10/2002	US6492664 Heterojunction bipolar transistor with reduced offset voltage
12/10/2002	US6492663 Universal source geometry for MOS-gated power devices
12/10/2002	US6492659 Semiconductor device having single crystal grains with hydrogen and tapered gate insulation layer
12/10/2002	US6492656 Reduced mask chalcogenide memory
12/10/2002	US6492643 X-ray image sensing device
12/10/2002	US6492285 High-pressure anneal process for integrated circuits
12/10/2002	US6492283 Method of forming ultrathin oxide layer
12/10/2002	US6492282 Integrated circuits and manufacturing methods
12/10/2002	US6492264 Semiconductor device having a silicide layer with silicon-rich region and method for making the same
12/10/2002	US6492250 Polycide gate structure and method of manufacture
12/10/2002	US6492249 High-K gate dielectric process with process with self aligned damascene contact to damascene gate and a low-k inter level dielectric
12/10/2002	US6492246 Method of forming a transistor in a semiconductor device
12/10/2002	US6492239 Method for fabricating avalanche photodiode
12/10/2002	US6492238 Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit
12/10/2002	US6492236 Method of manufacturing a semiconductor device with a silicide
12/10/2002	US6492232 Method of manufacturing vertical semiconductor device
12/10/2002	US6492231 Method of making triple self-aligned split-gate non-volatile memory device
12/10/2002	US6492230 Process for fabricating nonvolatile semiconductor memory with a selection transistor
12/10/2002	US6492228 Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
12/10/2002	US6492225 Method of fabricating enhanced EPROM structures with accentuated hot electron generation regions
12/10/2002	US6492220 Method for manufacturing semiconductor device capable of suppressing narrow channel width effect
12/10/2002	US6492218 Use of a hard mask in the manufacture of a semiconductor device
12/10/2002	US6492217 Complementary metal gates and a process for implementation
12/10/2002	US6492216 Method of forming a transistor with a strained channel
12/10/2002	US6492213 Semiconductor device, thin film transistor and method for producing the same, and liquid crystal display apparatus and method for producing the same
12/10/2002	US6492212 Variable threshold voltage double gated transistors and method of fabrication
12/10/2002	US6492210 Method for fully self-aligned FET technology
12/10/2002	US6492203 Semiconductor device and method of fabrication thereof
12/10/2002	US6492190 Method of producing electrooptical device and method of producing driving substrate for driving electrooptical device
12/10/2002	US6492122 Determining concentration of preferential nucleotide sequences in sample; obtain nucleotide sequences, amplify, hybridize with amplicons, detect and quantitate hybridization products
12/09/2002	CA2448006A1 High voltage, high temperature capacitor structures and methods of fabricating same
12/05/2002	WO2002098125A1 Signal processing circuit and solid-state image pickup device
12/05/2002	WO2002097900A2 Integrated tunable capacitor
12/05/2002	WO2002097899A2 Integrated tunable capacitor
12/05/2002	WO2002097898A1 High q varactor diodes
12/05/2002	WO2002097897A1 Semiconductor structure and method for improving its ability to withstand electrostatic discharge (esd) and overloads
12/05/2002	WO2002097896A1 Process for making a high voltage npn bipolar device with improved ac performance
12/05/2002	WO2002097895A2 Transistor, method for producing an integrated circuit and method for producing a metal silicide layer
12/05/2002	WO2002097891A2 Dram cell arrangement with vertical mos transistors and method for the production thereof
12/05/2002	WO2002097890A2 Bitline contacts in a memory cell array
12/05/2002	WO2002097888A1 Power semiconductor device
12/05/2002	WO2002097886A2 Semiconductor structure comprising an electrostatic discharge (esd) protection device
12/05/2002	WO2002097876A2 Manufacture of trench-gate field-effect transistors
12/05/2002	WO2002097861A2 Semiconductor device, semiconductor layer and production method thereof
12/05/2002	WO2002097820A2 Pair wise programming method for dual cell eeprom
12/05/2002	WO2002097724A1 Multi-feature-size electronic structures
12/05/2002	WO2002097173A2 Semi-insulating silicon carbide without vanadium domination
12/05/2002	WO2002096632A2 Dual-cell soft programming for virtual-ground memory arrays
12/05/2002	WO2002089192A8 Method of wet etching an inorganic antireflection layer
12/05/2002	WO2002069408A3 Soi ldmos transistor having a field plate and method of making the same
12/05/2002	WO2002050914A3 A semiconductor device with bias contact
12/05/2002	WO2002049114A3 High withstand voltage semiconductor device
12/05/2002	WO2002041403A3 Mos low-voltage vertical transistor
12/05/2002	WO2002037569A9 Trench gate mos semiconductor device
12/05/2002	WO2002019433A3 Trench schottky rectifier
12/05/2002	US20020183991 Method for modeling semiconductor device process

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