Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2013
05/16/2013US20130121798 Robot system with independent arms
05/16/2013US20130121792 Semiconductor manufacturing process module
05/16/2013US20130121509 Sound Transducer with Interdigitated First and Second Sets of Comb Fingers
05/16/2013US20130121087 Semiconductor manufacturing method
05/16/2013US20130121060 Non-volatile memory elements and memory devices including the same
05/16/2013US20130121056 Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
05/16/2013US20130121055 Word line driver cell layout for sram and other semiconductor devices
05/16/2013US20130120951 Stacked cmos chipset having an insulating layer and a secondary layer and method of forming same
05/16/2013US20130120896 Electrostatic chuck
05/16/2013US20130120732 Cylindrical magnetic levitation stage and lithography
05/16/2013US20130120731 Stage unit, exposure apparatus, and exposure method
05/16/2013US20130120699 Semiconductor device, method of manufacturing the device, and liquid crystal display
05/16/2013US20130120505 Bonded silicon structure for high density print head
05/16/2013US20130120327 Storage capacitor for electromechanical systems and methods of forming the same
05/16/2013US20130120018 Test Structure and Method of Testing Electrical Characteristics of Through Vias
05/16/2013US20130119688 Handling device for handling of a wafer
05/16/2013US20130119566 Semiconductor Chip and Substrate Transfer/Processing Tunnel -arrangement Extending in a Linear Direction
05/16/2013US20130119562 Semiconductor package, semiconductor package manufacturing method and semiconductor device
05/16/2013US20130119560 Packaging structural member
05/16/2013US20130119559 Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die
05/16/2013US20130119555 Through-Package-Via (TPV) Structures On Inorganic Interposer And Methods For Fabricating Same
05/16/2013US20130119553 Semiconductor package and method of manufacturing the same
05/16/2013US20130119552 Method for Forming Chip-on-Wafer Assembly
05/16/2013US20130119550 Semiconductor device and method of manufacturing the same
05/16/2013US20130119549 Mold Chase Design for Package-on-Package Applications
05/16/2013US20130119548 Method to fabricate high performance carbon nanotube transistor integrated circuits by three-dimensional integration technology
05/16/2013US20130119546 Semiconductor device and manufacturing method
05/16/2013US20130119545 Semiconductor device and method for forming the same
05/16/2013US20130119543 Through silicon via for stacked wafer connections
05/16/2013US20130119540 Semiconductor package and method for manufacturing the same
05/16/2013US20130119539 Package Structures and Methods for Forming the Same
05/16/2013US20130119538 Wafer level chip size package
05/16/2013US20130119535 Flip chip packages with improved thermal performance
05/16/2013US20130119533 Package for Three Dimensional Integrated Circuit
05/16/2013US20130119531 Semiconductor device and method for manufacturing the same
05/16/2013US20130119529 Semiconductor device having lid structure and method of making same
05/16/2013US20130119528 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
05/16/2013US20130119526 Lead frame, semiconductor manufacturing apparatus, and semiconductor device
05/16/2013US20130119525 Power Semiconductor Unit, Power Module, Power Semiconductor Unit Manufacturing Method, and Power Module Manufacturing Method
05/16/2013US20130119520 Chips with high fracture toughness through a metal ring
05/16/2013US20130119519 Composite substrate, electronic component, and method for manufacturing composite substrate, and method for manufacturing electronic component
05/16/2013US20130119518 Semiconductor formation by lateral diffusion liquid phase epitaxy
05/16/2013US20130119516 Pnp bipolar junction transistor fabrication using selective epitaxy
05/16/2013US20130119509 Forming beol line fuse structure
05/16/2013US20130119508 Bipolar junction transistor with multiple emitter fingers
05/16/2013US20130119507 Semiconductor device using group iii-v material and method of manufacturing the same
05/16/2013US20130119505 Schottky Barrier Diodes With a Guard Ring Formed by Selective Epitaxy
05/16/2013US20130119497 Magnetic tunnel junction structure
05/16/2013US20130119495 Magnetic tunnel junction devices having magnetic layers formed on composite, obliquely deposited seed layers
05/16/2013US20130119493 Microelectro mechanical system encapsulation scheme
05/16/2013US20130119491 Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure
05/16/2013US20130119490 Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
05/16/2013US20130119487 Structure and Method for MOSFETS with High-K and Metal Gate Structure
05/16/2013US20130119482 Fin field effect transistors and methods for fabricating the same
05/16/2013US20130119481 Finfet device
05/16/2013US20130119480 Integrated circuit resistor
05/16/2013US20130119478 Semiconductor device and manufacturing method thereof
05/16/2013US20130119477 Semiconductor device and manufacturing method thereof
05/16/2013US20130119474 Trench silicide and gate open with local interconnect with replacement gate process
05/16/2013US20130119473 Gate structures and methods of manufacture
05/16/2013US20130119470 Semiconductor device and method of manufacturing the same
05/16/2013US20130119468 Thin film transistor and method of fabricating the same
05/16/2013US20130119465 Dual channel trench ldmos transistors and transistors integrated therewith
05/16/2013US20130119462 Semiconductor device for increasing bit line contact area, and module and system including the same
05/16/2013US20130119460 Trench type power transistor device and fabricating method thereof
05/16/2013US20130119456 Semiconductor device and method for manufacturing the same
05/16/2013US20130119455 Nand flash with non-trapping switch transistors
05/16/2013US20130119451 Interlayer polysilicon dielectric cap and method of forming thereof
05/16/2013US20130119446 Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
05/16/2013US20130119445 Cmos device for reducing radiation-induced charge collection and method for fabricating the same
05/16/2013US20130119444 Semiconductor device and method of manufacturing the same
05/16/2013US20130119442 Junction field-effect transistor with raised source and drain regions formed by selective epitaxy
05/16/2013US20130119440 Biosensors integrated with a microfluidic structure
05/16/2013US20130119436 Interface control in a bipolar junction transistor
05/16/2013US20130119435 Dielectric dummification for enhanced planarization with spin-on dielectrics
05/16/2013US20130119434 Bipolar transistor with a collector having a protected outer edge portion for reduced based-collector junction capacitance and a method of forming the transistor
05/16/2013US20130119419 Magnetically adjusting color-converting materials within a matrix and associated devices, systems, and methods
05/16/2013US20130119408 Display Device and Method for Fabricating the Same
05/16/2013US20130119407 Method for manufacturing semiconductor device, and semiconductor device
05/16/2013US20130119406 Silicon carbide substrate, semiconductor device, and methods for manufacturing them
05/16/2013US20130119404 Device structure including high-thermal-conductivity substrate
05/16/2013US20130119401 Large area nitride crystal and method for making it
05/16/2013US20130119394 Termination Structure for Gallium Nitride Schottky Diode
05/16/2013US20130119393 Vertical Gallium Nitride Schottky Diode
05/16/2013US20130119392 Organic light-emitting display device and method of manufacturing the same
05/16/2013US20130119383 Semiconductor device and electronic unit
05/16/2013US20130119382 Plating Process and Structure
05/16/2013US20130119377 Semiconductor device and method of manufacturing semiconductor device
05/16/2013US20130119375 Semiconductor device and method for manufacturing semiconductor device
05/16/2013US20130119349 Graphene transistor having air gap, hybrid transistor having the same, and methods of fabricating the same
05/16/2013US20130119347 Semiconductor device including group iii-v barrier and method of manufacturing the semiconductor device
05/16/2013US20130119251 Method and apparatus for charged particle beam inspection
05/16/2013US20130118895 Apparatus and method for reactive ion etching
05/16/2013US20130118688 Etching apparatus
05/16/2013US20130118536 Ultrasonic precision cleaning apparatus
05/16/2013US20130118404 Methods and Systems for Forming Thin Films
05/16/2013DE112011102417T5 Herstellung von polykristallinem Silizium Producing polycrystalline silicon
05/16/2013DE112011102300T5 Verfahren zur elektrolytischen Abscheidung von Gallium- und Galliumlegierungs-Dünnschichten und zugehöriger Photovoltaikstrukturen A method for the electrolytic deposition of gallium and Galliumlegierungs thin films and related photovoltaic structures
05/16/2013DE112011101976T5 Verfahren für das selektive Ätzen eines Isolatorstapels für einen Metallverbinder Method for the selective etching of an insulator stack for a metal connector
05/16/2013DE112010005681T5 Leistungshalbleiterbauteil Power semiconductor component