Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2013
05/28/2013US8450199 Integrating diverse transistors on the same wafer
05/28/2013US8450198 Graphene based switching device having a tunable bandgap
05/28/2013US8450197 Contact elements of a semiconductor device formed by electroless plating and excess material removal with reduced sheer forces
05/28/2013US8450196 Production of an integrated circuit including electrical contact on SiC
05/28/2013US8450195 Method of reducing floating body effect of SOI MOS device via a large tilt ion implantation
05/28/2013US8450194 Method to modify the shape of a cavity using angled implantation
05/28/2013US8450193 Techniques for temperature-controlled ion implantation
05/28/2013US8450192 Growth of planar, non-polar, group-III nitride films
05/28/2013US8450191 Polysilicon films by HDP-CVD
05/28/2013US8450190 Fabrication of GaN substrate by defect selective passivation
05/28/2013US8450189 Film for flip chip type semiconductor back surface
05/28/2013US8450188 Method of removing back metal from an etched semiconductor scribe street
05/28/2013US8450187 Method of cutting semiconductor substrate
05/28/2013US8450186 Optical modulator utilizing wafer bonding technology
05/28/2013US8450185 Semiconductor structures having directly bonded diamond heat sinks and methods for making such structures
05/28/2013US8450184 Thin substrate fabrication using stress-induced spalling
05/28/2013US8450183 Power semiconductor device and method of manufacturing the same
05/28/2013US8450181 In-situ passivation methods to improve performance of polysilicon diode
05/28/2013US8450180 Methods of forming semiconductor trench and forming dual trenches, and structure for isolating devices
05/28/2013US8450179 Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication
05/28/2013US8450178 Borderless contacts for semiconductor devices
05/28/2013US8450177 LDMOS with self aligned vertical LDD backside drain
05/28/2013US8450176 Methods of manufacturing rewriteable three-dimensional semiconductor memory devices
05/28/2013US8450175 Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith
05/28/2013US8450174 Non-volatile storage having a connected source and well
05/28/2013US8450173 Electrical components for microelectronic devices and methods of forming the same
05/28/2013US8450172 Non-insulating stressed material layers in a contact level of semiconductor devices
05/28/2013US8450171 Strained semiconductor device and method of making same
05/28/2013US8450170 Semiconductor memory device and method of forming the same
05/28/2013US8450169 Replacement metal gate structures providing independent control on work function and gate leakage current
05/28/2013US8450168 Ferro-electric capacitor modules, methods of manufacture and design structures
05/28/2013US8450167 Method of fabricating semiconductor devices
05/28/2013US8450166 Method of fabricating semiconductor devices
05/28/2013US8450165 Semiconductor device having tipless epitaxial source/drain regions
05/28/2013US8450164 Methods of forming a plurality of capacitors
05/28/2013US8450163 Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach
05/28/2013US8450162 HBT and field effect transistor integration
05/28/2013US8450161 Method of fabricating a sealing structure for high-k metal gate
05/28/2013US8450160 Flattening method of a substrate
05/28/2013US8450159 Thin film transistor, fabrication method of same, and display device having the same
05/28/2013US8450158 Method for forming microcrystalline semiconductor film and method for manufacturing semiconductor device
05/28/2013US8450156 Method for producing a thyristor
05/28/2013US8450155 Method for introducing channel stress and field effect transistor fabricated by the same
05/28/2013US8450154 Oxide based memory with a controlled oxygen vacancy conduction path
05/28/2013US8450152 Double-side exposed semiconductor device and its manufacturing method
05/28/2013US8450150 Manufacturing method of semiconductor integrated circuit device
05/28/2013US8450149 Stacked leadframe implementation for DC/DC convertor power module incorporating a stacked controller and stacked leadframe construction methodology
05/28/2013US8450148 Molding compound adhesion for map-molded flip-chip
05/28/2013US8450147 Laminating encapsulant film containing phosphor over LEDs
05/28/2013US8450146 Transistor assembly and method for manufacturing the same
05/28/2013US8450145 Nonvolatile semiconductor memory device and method for producing the same
05/28/2013US8450144 Semiconductor device and method for manufacturing the same
05/28/2013US8450142 Organic thin film transistors
05/28/2013US8450141 Processes for fabricating all-back-contact heterojunction photovoltaic cells
05/28/2013US8450140 Method for large-scale manufacturing of photovoltaic cells for a converter panel and photovoltaic converter panel
05/28/2013US8450138 Three-dimensional bicontinuous heterostructures, method of making, and their application in quantum dot-polymer nanocomposite photodetectors and photovoltaics
05/28/2013US8450137 Method for reducing tilt of transparent window during manufacturing of image sensor
05/28/2013US8450133 Strained-enhanced silicon photon-to-electron conversion devices
05/28/2013US8450132 Thermally activated micromirror and fabrication method
05/28/2013US8450131 Imprinted semiconductor multiplex detection array
05/28/2013US8450130 Method of manufacturing a semiconductor laser
05/28/2013US8450128 Method for producing semiconductor optical device and semiconductor optical device
05/28/2013US8450127 Light emitting semiconductor diode
05/28/2013US8450126 Semiconductor test pad structures
05/28/2013US8450125 Methods of evaluating epitaxial growth and methods of forming an epitaxial layer
05/28/2013US8450123 Oxygen diffusion evaluation method of oxide film stacked body
05/28/2013US8450122 Test structures and methods
05/28/2013US8450120 SEM repair for sub-optimal features
05/28/2013US8450119 Magnetic tunnel junction patterning using Ta/TaN as hard mask
05/28/2013US8449806 Laser processing apparatus
05/28/2013US8449805 Masking techniques and contact imprint reticles for dense semiconductor fabrication
05/28/2013US8449731 Method and apparatus for increasing local plasma density in magnetically confined plasma
05/28/2013US8449715 Internal member of a plasma processing vessel
05/28/2013US8449684 Substrate cleaning method, substrate cleaning system and program storage medium
05/28/2013US8449678 Combinatorial process system
05/28/2013US8448333 Method for manufacturing wiring board and method for manufacturing inkjet printhead substrate
05/28/2013US8448288 Semiconductor equipment
05/28/2013CA2628812C Apparatus for imprinting and/or embossing substrates
05/28/2013CA2520241C Metal base circuit board and its production process
05/23/2013WO2013074752A1 Laser scribing systems, apparatus, and methods
05/23/2013WO2013074707A1 Systems and methods for substrate polishing detection using improved friction measurement
05/23/2013WO2013074706A1 Systems and methods for substrate polishing end point detection using improved friction measurement
05/23/2013WO2013074622A1 Method for patterning an organic material using a non-fluorinated photoresist
05/23/2013WO2013074543A1 High throughput hot testing method and system for high brightness light emitting diodes
05/23/2013WO2013074523A1 Ion implant apparatus and a method of implanting ions
05/23/2013WO2013074376A1 Method of transferring a light emitting diode
05/23/2013WO2013074373A1 Micro device transfer head heater assembly and method of transferring a micro device
05/23/2013WO2013074369A1 Method and apparatus for selective nitridation process
05/23/2013WO2013074357A1 Method of transferring a micro device
05/23/2013WO2013074356A1 Method of fabricating a micro device transfer head
05/23/2013WO2013074355A1 Micro device transfer head
05/23/2013WO2013074353A1 Memory cells, integrated devices, and methods of forming memory cells
05/23/2013WO2013074339A1 Doping aluminum in tantalum silicide
05/23/2013WO2013074306A1 Method and apparatus providing single step cadmium chloride vapour treatment for photovoltaic modules
05/23/2013WO2013074298A1 Defected ground plane inductor
05/23/2013WO2013074278A1 Process to remove ni and pt residues for niptsi applications
05/23/2013WO2013074235A1 Electrical overstress protection using through-silicon-via (tsv)
05/23/2013WO2013074169A1 Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for cmos devices
05/23/2013WO2013074076A1 Macro-transistor devices
05/23/2013WO2013074061A1 Controlled solder-on-die integrations on packages and methods of assembling same