| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
|---|
| 01/07/1998 | EP0815501A2 Apparatus and method for controlling high throughput sputtering |
| 01/07/1998 | EP0815494A1 Scanning lithography system with opposing motion |
| 01/07/1998 | EP0815481A2 Magnification correction for small field scanning |
| 01/07/1998 | EP0815480A2 Scanning lithography system having double pass wynne-dyson optics |
| 01/07/1998 | EP0782719A4 Protective mask for pellicle |
| 01/07/1998 | EP0779989A4 Membrane probing of circuits |
| 01/07/1998 | EP0779987A4 Membrane probing of circuits |
| 01/07/1998 | EP0741909A4 Methods for improving semiconductor processing |
| 01/07/1998 | EP0648698B1 Magnetically levitated carrying apparatus |
| 01/07/1998 | EP0591414B1 Lead frame for integrated circuits or the like |
| 01/07/1998 | CN1169799A Electrostatic discharge circuit for high speed, high voltage cricuit |
| 01/07/1998 | CN1169796A Method for purging a multi-layer sacrificial etched silicon substrate |
| 01/07/1998 | CN1169595A Sram cell and method of manufacturing the same |
| 01/07/1998 | CN1169594A Semiconductor device |
| 01/07/1998 | CN1169591A Die-bonding device |
| 01/07/1998 | CN1169590A Method and equipment of planarizing interlayer dielectric |
| 01/07/1998 | CN1169589A Semiconductor device and mfg. method thereof |
| 01/07/1998 | CN1169578A Semiconductor memory device |
| 01/07/1998 | CN1169560A Logical check apparatus for semiconductor circuits |
| 01/07/1998 | CN1169546A Phase shift mask and method for fabricating same |
| 01/07/1998 | CN1169452A Solvent-free epoxy based adhesives for semiconductor chip attachment and process for preparing same |
| 01/06/1998 | US5706403 Semiconductor neural circuit device |
| 01/06/1998 | US5706295 Method of checking design rules for semiconductor integrated circuit |
| 01/06/1998 | US5706294 Method of finding DC test point of an integrated circuit |
| 01/06/1998 | US5706292 Layout for a semiconductor memory device having redundant elements |
| 01/06/1998 | US5706241 Eeprom semiconductor memory device including circuit for generating a voltage higher than a power supply voltage |
| 01/06/1998 | US5706233 Semiconductor memory device allowing acceleration testing, and a semi-finished product for an integrated semiconductor device that allows acceleration testing |
| 01/06/1998 | US5706229 Semiconductor memory device |
| 01/06/1998 | US5706206 Method of extracting parasitic capacitance values from the physical design of an integrated circuit |
| 01/06/1998 | US5706201 Software to determine the position of the center of a wafer |
| 01/06/1998 | US5706176 Butted chip array with beveled chips |
| 01/06/1998 | US5706175 Resin-sealed semiconductor device |
| 01/06/1998 | US5706174 Compliant microelectrionic mounting device |
| 01/06/1998 | US5706164 Method of fabricating high density integrated circuits, containing stacked capacitor DRAM devices, using elevated trench isolation and isolation spacers |
| 01/06/1998 | US5706156 Semiconductor device having an ESD protective circuitry |
| 01/06/1998 | US5706094 Ultrafast optical technique for the characterization of altered materials |
| 01/06/1998 | US5706077 Scan type projection exposure apparatus and microdevice manufacturing method using the same |
| 01/06/1998 | US5706076 Semiconductor light exposure apparatus |
| 01/06/1998 | US5705941 Output driver for use in semiconductor integrated circuit |
| 01/06/1998 | US5705935 Method of managing mapping data indicative of excellent/defective chips on semiconductor wafer |
| 01/06/1998 | US5705934 Integrated circuit |
| 01/06/1998 | US5705925 Analog autonomous test bus framework for testing integrated circuits on a printed circuit board |
| 01/06/1998 | US5705858 Packaging structure for a hermetically sealed flip chip semiconductor device |
| 01/06/1998 | US5705856 Semiconductor device |
| 01/06/1998 | US5705855 For displaying information to a user |
| 01/06/1998 | US5705849 Antifuse structure and method for manufacturing it |
| 01/06/1998 | US5705847 Semiconductor device |
| 01/06/1998 | US5705845 Semiconductor device with particular metal silicide film |
| 01/06/1998 | US5705843 Integrated circuits and SRAM memory cells |
| 01/06/1998 | US5705840 Field effect transistor with recessed buried source and drain regions |
| 01/06/1998 | US5705839 Gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology |
| 01/06/1998 | US5705838 Array of bit line over capacitor array of memory cells |
| 01/06/1998 | US5705830 Static induction transistors |
| 01/06/1998 | US5705829 Semiconductor device formed using a catalyst element capable of promoting crystallization |
| 01/06/1998 | US5705825 Resonant tunneling bipolar transistor |
| 01/06/1998 | US5705570 Acrylate polymers |
| 01/06/1998 | US5705443 Etching method for refractory materials |
| 01/06/1998 | US5705442 Optimized tungsten contact plug process via use of furnace annealed barrier layers |
| 01/06/1998 | US5705441 Ion implant silicon nitride mask for a silicide free contact region in a self aligned silicide process |
| 01/06/1998 | US5705440 Methods of fabricating integrated circuit field effect transistors having reduced-area device isolation regions |
| 01/06/1998 | US5705439 Method to make an asymmetrical LDD structure for deep sub-micron MOSFETS |
| 01/06/1998 | US5705438 Method for manufacturing stacked dynamic random access memories using reduced photoresist masking steps |
| 01/06/1998 | US5705437 Trench free process for SRAM |
| 01/06/1998 | US5705436 Method for forming a poly load resistor |
| 01/06/1998 | US5705435 Detecting endpoint without removing substrate |
| 01/06/1998 | US5705433 Adding silicon hydride gas to halogen etchant |
| 01/06/1998 | US5705432 Process for providing clean lift-off of sputtered thin film layers |
| 01/06/1998 | US5705431 Production method for insulated semiconductor device |
| 01/06/1998 | US5705430 Dual damascene with a sacrificial via fill |
| 01/06/1998 | US5705429 Method of manufacturing aluminum wiring at a substrate temperature from 100 to 150 degrees celsius |
| 01/06/1998 | US5705428 Method for preventing titanium lifting during and after metal etching |
| 01/06/1998 | US5705427 Method of forming a landing pad structure in an integrated circuit |
| 01/06/1998 | US5705426 Method of forming semiconductor device having planarized wiring with good thermal resistance |
| 01/06/1998 | US5705425 Process for manufacturing semiconductor devices separated by an air-bridge |
| 01/06/1998 | US5705424 Process of fabricating active matrix pixel electrodes |
| 01/06/1998 | US5705423 Epitaxial wafer |
| 01/06/1998 | US5705422 Method for forming well of semiconductor device |
| 01/06/1998 | US5705421 A SOI substrate fabricating method |
| 01/06/1998 | US5705420 Method of producing a fin-shaped capacitor |
| 01/06/1998 | US5705419 Controllable isotropic plasma etching technique for the suppression of stringers in memory cells |
| 01/06/1998 | US5705418 Process for fabricating reduced-thickness high-resistance load resistors in four-transistor SRAM devices |
| 01/06/1998 | US5705417 Method for forming self-aligned silicide structure |
| 01/06/1998 | US5705416 Method of manufacturing a flash EEPROM cell |
| 01/06/1998 | US5705415 Process for forming an electrically programmable read-only memory cell |
| 01/06/1998 | US5705414 Method for producing a gate electrode for an MOS structure |
| 01/06/1998 | US5705413 Method of manufacturing an electronic device using thermally stable mask |
| 01/06/1998 | US5705412 Method of making buried gate insulator field effect transistor |
| 01/06/1998 | US5705410 Method of producing a semi-conductor with a highly doped zone situated between lightly doped zones, for the manufacture of transistors |
| 01/06/1998 | US5705409 Method for forming trench transistor structure |
| 01/06/1998 | US5705408 Method for forming semiconductor integrated circuit using monolayer epitaxial growth |
| 01/06/1998 | US5705407 Method of forming high performance bipolar devices with improved wiring options |
| 01/06/1998 | US5705406 Method for producing a semiconductor device having semiconductor layers of SiC by the use of an ion-implantation technique |
| 01/06/1998 | US5705405 Method of making the film transistor with all-around gate electrode |
| 01/06/1998 | US5705404 Method of implant verification in semiconductor device using reticle specific indicator |
| 01/06/1998 | US5705403 Concentration, lasers |
| 01/06/1998 | US5705321 Method for manufacture of quantum sized periodic structures in Si materials |
| 01/06/1998 | US5705319 Process for forming fine patterns for a semiconductor device utilizing three photosensitive layers |
| 01/06/1998 | US5705300 Quartz substrate with grooves, chromium pattern coating and phase shift material |
| 01/06/1998 | US5705232 In-situ coat, bake and cure of dielectric material processing system for semiconductor manufacturing |
| 01/06/1998 | US5705230 Method for filling small holes or covering small recesses in the surface of substrates |