Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/1998
06/02/1998US5760693 Vacuum apparatus for semiconductor device
06/02/1998US5760650 Coplanar waveguide amplifier
06/02/1998US5760642 Filter circuit using a junction capacitor of a semiconductor
06/02/1998US5760631 Protection circuit for a CMOS integrated circuit
06/02/1998US5760630 In a semiconductor integrated circuit
06/02/1998US5760604 Interconnect architecture for field programmable gate array
06/02/1998US5760602 Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA
06/02/1998US5760600 Test device for insulated-gate field effect transistor and testing circuit and testing method using the same
06/02/1998US5760599 Method and apparatus for testing semiconductor integrated circuits
06/02/1998US5760597 Method of and apparatus for measuring lifetime of carriers in semiconductor sample
06/02/1998US5760594 Contamination monitoring using capacitance measurements on MOS structures
06/02/1998US5760564 Dual guide beam stage mechanism with yaw control
06/02/1998US5760561 Method of controlling a stage and a system such as an exposing apparatus using the same
06/02/1998US5760482 Semiconductor device of the type sealed in glass comprising a semiconductor body connected to slugs by means of a silver-aluminum bonding layer
06/02/1998US5760480 Low RC interconnection
06/02/1998US5760478 Clock skew minimization system and method for integrated circuits
06/02/1998US5760477 Integrated circuit contacts having resistive electromigration characteristics
06/02/1998US5760476 Interconnect run between a first point and a second point in a semiconductor device for reducing electromigration failure
06/02/1998US5760475 Refractory metal-titanium nitride conductive structures
06/02/1998US5760474 Capacitor, integrated circuitry, diffusion barriers, and method for forming an electrically conductive diffusion barrier
06/02/1998US5760465 Electronic package with strain relief means
06/02/1998US5760461 Vertical mask for defining a region on a wall of a semiconductor structure
06/02/1998US5760459 High performance, high voltage non-epibipolar transistor
06/02/1998US5760458 Bipolar-based active pixel sensor cell with poly contact and increased capacitive coupling to the base region
06/02/1998US5760457 Bipolar transistor circuit element having base ballasting resistor
06/02/1998US5760454 Pattern form of an active region of a MOS type semiconductor device
06/02/1998US5760451 Raised source/drain with silicided contacts for semiconductor devices
06/02/1998US5760450 Semiconductor resistor using back-to-back zener diodes
06/02/1998US5760447 Semiconductor device having pull-up or pull-down resistance
06/02/1998US5760446 Electrostatic discharge structure of semiconductor device
06/02/1998US5760445 Device and method of manufacture for protection against plasma charging damage in advanced MOS technologies
06/02/1998US5760444 Silicon on insulator type semiconductor device
06/02/1998US5760443 Silicon on insulator with active buried regions
06/02/1998US5760442 Semiconductor device of a silicon on insulator metal-insulator type with a concave feature
06/02/1998US5760441 Metal oxide semiconductor device
06/02/1998US5760440 Back-source MOSFET
06/02/1998US5760439 Semiconductor memory device
06/02/1998US5760437 Semiconductor memory device, a method for manufacturing thereof and a connecting method of virtual ground array of a semiconductor memory device
06/02/1998US5760436 EEPROM cell and process for formation thereof
06/02/1998US5760435 Use of spacers as floating gates in EEPROM with doubled storage efficiency
06/02/1998US5760434 Increased interior volume for integrated memory cell
06/02/1998US5760433 In situ reactive layers for protection of ferroelectric integrated circuits
06/02/1998US5760432 Thin film strained layer ferroelectric capacitors
06/02/1998US5760430 Charge transfer device and solid-state imaging apparatus using the same device
06/02/1998US5760429 Multi-layer wiring structure having varying-sized cutouts
06/02/1998US5760428 Variable width low profile gate array input/output architecture
06/02/1998US5760427 High electron mobility transistor with an improved interface between donor and schottky layers
06/02/1998US5760426 Heteroepitaxial semiconductor device including silicon substrate, GaAs layer and GaN layer #13
06/02/1998US5760425 Internal compression bonded semiconductor device with a chip frame enabling a longer creepage distance
06/02/1998US5760421 Semiconductor device including indices for identifying positions of elements in the device.
06/02/1998US5760418 GaAs power semiconductor device operating at a low voltage and method for fabricating the same
06/02/1998US5760411 Alignment method for positioning a plurality of shot areas on a substrate
06/02/1998US5760410 For drawing an exposure pattern on a sample
06/02/1998US5760409 Dose control for use in an ion implanter
06/02/1998US5760408 Semiconductor exposure device
06/02/1998US5760405 Plasma chamber for controlling ion dosage in ion implantation
06/02/1998US5760337 Binder consists of crosslinked resin produced by reacting atleast one dienophile having functionality greater than one and atleast one polymer formed by reacting cabon monoxide and aliphatic alpha-olefin and a filler
06/02/1998US5759971 Semiconductor wafer cleaning liquid
06/02/1998US5759923 Flowing mist of liquid precursor to form layer on substrate; treating to solidify
06/02/1998US5759922 Eliminates notching: exposing wafer to chlorine plasma under conditions which reduce the relative role of ions (as compared to neutrals) in the etch; eliminating magnetic field confinement in transition zone
06/02/1998US5759921 Integrated circuit device fabrication by plasma etching
06/02/1998US5759920 First reactive ion etching for high etch rate of polysilicon film; second reactive ion etching is a low polysilicon etch rate process; non-uniformities of surface are removed by sputtering
06/02/1998US5759919 Method for reducing gate oxide damages during gate electrode plasma etching
06/02/1998US5759918 Method for chemical mechanical polishing
06/02/1998US5759917 Composition for oxide CMP
06/02/1998US5759916 Method for forming a void-free titanium nitride anti-reflective coating(ARC) layer upon an aluminum containing conductor layer
06/02/1998US5759915 Method of forming semiconductor device having an improved buried electrode formed by selective CVD
06/02/1998US5759914 Multiple layering and patterning to ensure connection
06/02/1998US5759913 Method of formation of an air gap within a semiconductor dielectric by solvent desorption
06/02/1998US5759912 Method of manufacturing a semiconductor device having multi-layered wiring without hillocks at the insulating layers
06/02/1998US5759911 Filling undesired sublithographic contact hole defects in a semiconductor
06/02/1998US5759910 Process for fabricating a solder bump for a flip chip integrated circuit
06/02/1998US5759909 Method for manufacturing a silicon wafer by using a dopant foil
06/02/1998US5759908 Method for forming SiC-SOI structures
06/02/1998US5759907 Method of making large value capacitor for SOI
06/02/1998US5759906 Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits
06/02/1998US5759905 Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening
06/02/1998US5759904 Bombarding silicon substrate in vacuum witrh a beam of helium ions to form dipsersed bubbles at same depth to which dopants will penetrate for damage prevention
06/02/1998US5759903 Doped, single-crystal silicon substrate; hole openings produced by electrochemical etching in a fluoride-containing, acidic electrolyte where substrate is connected as anode
06/02/1998US5759902 Method of making an integrated circuit with complementary junction-isolated bipolar transistors
06/02/1998US5759901 Graded source and drain impurity regions comprise a relatively linear continuum of doped regions, ranging from lightly doped, to moderately doped to heavily doped regions
06/02/1998US5759900 Method for manufacturing MOSFET
06/02/1998US5759899 Method of fabricating semiconductor device having a salicide structure
06/02/1998US5759898 Production of substrate for tensilely strained semiconductor
06/02/1998US5759897 Method of making an asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region
06/02/1998US5759896 Preventing defects during storage or erasing by use of lower voltages
06/02/1998US5759895 Method of fabricating a capacitor storage node having a rugged-fin surface
06/02/1998US5759894 Method for forming a DRAM capacitor using HSG-Si
06/02/1998US5759893 Selectively etching doped and undoped polysilicon layers by a hot phosphoric acid solution
06/02/1998US5759892 Formation of self-aligned capacitor contact module in stacked cyclindrical dram cell
06/02/1998US5759891 Increased surface area capacitor via use of a novel reactive ion etch procedure
06/02/1998US5759890 Method for fabricating a tree-type capacitor structure for a semiconductor memory device
06/02/1998US5759889 Heating refractory metal layer so that metal silicide layers are formed in bit line
06/02/1998US5759888 Method for fabricating a DRAM cell with a Y shaped storage capacitor
06/02/1998US5759887 Using silicon nitride dielectric and concurrent resist patterning for capacitor and resistor
06/02/1998US5759886 Layer of dielectric is deposited and baked to densify and reflow the dielectric; etching; metallization; degradation of metallic layer from baking is eliminated
06/02/1998US5759885 Method for fabricating CMOSFET having LDD structure
06/02/1998US5759884 Method for forming well of semiconductor device
06/02/1998US5759883 Method for making semiconductor device capable of independently forming MOS transistors and bipolar transistor
06/02/1998US5759882 Method of fabricating self-aligned contacts and local interconnects in CMOS and BICMOS processes using chemical mechanical polishing (CMP)
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