| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 06/16/1998 | US5767571 Semiconductor device and display unit using the semiconductor device and notebook-size personal computer |
| 06/16/1998 | US5767570 Semiconductor packages for high I/O semiconductor dies |
| 06/16/1998 | US5767569 Tab tape and semiconductor chip mounted on tab tape |
| 06/16/1998 | US5767568 Semiconductor device |
| 06/16/1998 | US5767566 Plastic mold type semiconductor device |
| 06/16/1998 | US5767562 Dielectrically isolated power IC |
| 06/16/1998 | US5767561 Integrated circuit device with isolated circuit elements |
| 06/16/1998 | US5767558 Semiconductor device fabricated in such manner that reduced diffusion of fluorine from tungsten fluoride into silicon gate occurs |
| 06/16/1998 | US5767557 PMOSFETS having indium or gallium doped buried channels and n+polysilicon gates and CMOS devices fabricated therefrom |
| 06/16/1998 | US5767553 Flat cell mask ROM having compact select transistor structure |
| 06/16/1998 | US5767552 Structure for ESD protection in semiconductor chips |
| 06/16/1998 | US5767551 Intergrated circuit combining high frequency bipolar and high power CMOS transistors |
| 06/16/1998 | US5767548 Semiconductor component with embedded fixed charges to provide increased high breakdown voltage |
| 06/16/1998 | US5767547 High voltage thin film transistor having a linear doping profile |
| 06/16/1998 | US5767546 Laternal power mosfet having metal strap layer to reduce distributed resistance |
| 06/16/1998 | US5767544 Semiconductor integrated circuit device |
| 06/16/1998 | US5767543 Ferroelectric semiconductor device having a layered ferroelectric structure |
| 06/16/1998 | US5767541 Semiconductor memory device with ferroelectric capacitor |
| 06/16/1998 | US5767540 Hetero-junction bipolar transistor having AlGaAsP emitter layer underneath a base electrode |
| 06/16/1998 | US5767536 Having electrode which shows small contact resistance and enables an ohmic contact between electrode and a semiconductor layer; layer comprises zinc, magnesium, sulfur, selenium |
| 06/16/1998 | US5767535 Quantum layer structure |
| 06/16/1998 | US5767533 High-conductivity semiconductor material having a dopant comprising coulombic pairs of elements |
| 06/16/1998 | US5767531 Thin-film transistor, method of fabricating the same, and liquid-crystal display apparatus |
| 06/16/1998 | US5767530 Thin film transistor with reduced leakage current |
| 06/16/1998 | US5767529 Method of manufacturing a semiconductor |
| 06/16/1998 | US5767528 Semiconductor device including pad portion for testing |
| 06/16/1998 | US5767527 Semiconductor device suitable for testing |
| 06/16/1998 | US5767523 Multiple detector alignment system for photolithography |
| 06/16/1998 | US5767522 Ion-implantation system using split ion beams |
| 06/16/1998 | US5767521 Electron-beam lithography system and method for drawing nanometer-order pattern |
| 06/16/1998 | US5767516 Electron microscope and sample observing method using the same |
| 06/16/1998 | US5767503 Method for the manufacture of contact-free cards |
| 06/16/1998 | US5767486 Rapid thermal heating apparatus including a plurality of radiant energy sources and a source of processing gas |
| 06/16/1998 | US5767480 Hole generation and lead forming for integrated circuit lead frames using laser machining |
| 06/16/1998 | US5767446 Printed circuit board having epoxy barrier around a throughout slot and ball grid array semiconductor package |
| 06/16/1998 | US5767302 High-purity TI complexes, methods for producing the same and BST film-forming liquid compositions |
| 06/16/1998 | US5767301 Copper hexafluoroacetylacetonate with ethoxyvinylsilane ligand; chemical vapor deposition |
| 06/16/1998 | US5767292 Processes for preparing 1-methoxy-2-propyl 3-(7-diethylamino-2-oxo-2H-chromen-3-yl)-3-oxopropionate |
| 06/16/1998 | US5767048 Dipping printed circuit board into halogen-free solvent mixture containing hydrocarbon and a metal complexing pyrrolidone, phosphine oxide or sulfoxide compound to dissolve adhered solder flux |
| 06/16/1998 | US5767021 Dry etching method, chemical vapor deposition method, and apparatus for processing semiconductor substrate |
| 06/16/1998 | US5767020 Using as etchant hydrofluoric acid and hydrogen peroxide |
| 06/16/1998 | US5767019 Method for forming a fine contact hole in a semiconductor device |
| 06/16/1998 | US5767018 Method of etching a polysilicon pattern |
| 06/16/1998 | US5767017 Selective removal of vertical portions of a film |
| 06/16/1998 | US5767016 Method of forming a wiring layer on a semiconductor by polishing with treated slurry |
| 06/16/1998 | US5767015 Metal plug with adhesion layer |
| 06/16/1998 | US5767014 Dielectric material is the reaction product of a hyperbranced polymer and a polysilsesquioxane |
| 06/16/1998 | US5767013 Forming conductive layer on substrate, polishing to form rugged surface, selectively removing polished layer to form interconnection pattern; reduction of metallic reflection |
| 06/16/1998 | US5767012 Forming conductors on substrate, forming dielectric, forming trench, planarizing conductive material, etching, forming second dielectric layer |
| 06/16/1998 | US5767010 Solder bump fabrication methods and structure including a titanium barrier layer |
| 06/16/1998 | US5767009 Structure of chip on chip mounting preventing from crosstalk noise |
| 06/16/1998 | US5767008 Method for forming a gold plating electrode, a substrate based on the electrode forming method, and a wire bonding method utilizing this electrode forming method |
| 06/16/1998 | US5767007 Method for fabricating ohmic electrode and multi-layered structure for ohmic fabricating electrode |
| 06/16/1998 | US5767006 Method for eliminating charge damage during etching of conducting layers |
| 06/16/1998 | US5767005 Method for fabricating a flash EEPROM |
| 06/16/1998 | US5767004 Forming amorphous silicon layer on substrate, forming polysilicon layer, annealing, forming impurity diffusion inhibiting layer |
| 06/16/1998 | US5767003 Thin film semiconductor device manufacturing method |
| 06/16/1998 | US5767002 Method of manufacturing a multi-layer film each layer having single-layer area |
| 06/16/1998 | US5767001 Process for producing semiconductor components between which contact is made vertically |
| 06/16/1998 | US5767000 Method of manufacturing subfield conductive layer |
| 06/16/1998 | US5766999 Method for making self-aligned bipolar transistor |
| 06/16/1998 | US5766998 Resolution |
| 06/16/1998 | US5766997 Method of forming floating gate type non-volatile semiconductor memory device having silicided source and drain regions |
| 06/16/1998 | US5766996 Forming multilayer structure on substrate, coating with oxidation resistant layer, forming oxide layer |
| 06/16/1998 | US5766995 Method for forming a DRAM cell with a ragged polysilicon crown-shaped capacitor |
| 06/16/1998 | US5766994 Dynamic random access memory fabrication method having stacked capacitors with increased capacitance |
| 06/16/1998 | US5766993 Method of fabricating storage node electrode, for DRAM devices, using polymer spacers, to obtain polysilicon columns, with minimum spacing between columns |
| 06/16/1998 | US5766992 Forming field oxide regions, insulator layer, polysilicon layer, doping, depositing silicon nitride, patterning, etching |
| 06/16/1998 | US5766991 CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain |
| 06/16/1998 | US5766990 Method of manufacturing a high speed bipolar transistor in a CMOS process |
| 06/16/1998 | US5766989 Method for forming polycrystalline thin film and method for fabricating thin-film transistor |
| 06/16/1998 | US5766988 Fabricating method for a thin film transistor with a negatively sloped gate |
| 06/16/1998 | US5766987 Microelectronic encapsulation methods and equipment |
| 06/16/1998 | US5766986 Method of transfer molding electronic packages and packages produced thereby |
| 06/16/1998 | US5766985 Process for encapsulating a semiconductor device having a heat sink |
| 06/16/1998 | US5766984 Method of making a vertical integrated circuit |
| 06/16/1998 | US5766983 Tape automated bonding circuit with interior sprocket holes |
| 06/16/1998 | US5766982 Method and apparatus for underfill of bumped or raised die |
| 06/16/1998 | US5766981 Thermally processed, phosphorus- or arsenic-containing semiconductor laser with selective IILD |
| 06/16/1998 | US5766979 Wafer level contact sheet and method of assembly |
| 06/16/1998 | US5766977 Generating a hydrogen active material by reacting heated nickel and hydrogen gas, annealing |
| 06/16/1998 | US5766976 Method for detecting crystal defects in a silicon single crystal substrate |
| 06/16/1998 | US5766975 Packaged integrated circuit having thermal enhancement and reduced footprint size |
| 06/16/1998 | US5766974 Silicon oxynitride layer |
| 06/16/1998 | US5766973 Method for manufacturing a semiconductor arrangement by introducing crystal disorder structures and varying diffusion rates |
| 06/16/1998 | US5766972 Method of making resin encapsulated semiconductor device with bump electrodes |
| 06/16/1998 | US5766971 Forming oxide on substrate, etching to form isolation trench, filling with oxide, etching, reacting with ammonia to form nitride, etching |
| 06/16/1998 | US5766970 Method of manufacturing a twin well semiconductor device with improved planarity |
| 06/16/1998 | US5766969 Multiple spacer formation/removal technique for forming a graded junction |
| 06/16/1998 | US5766968 Micro mask comprising agglomerated material |
| 06/16/1998 | US5766967 For field effect transistors |
| 06/16/1998 | US5766966 Power transistor device having ultra deep increased concentration region |
| 06/16/1998 | US5766965 Forming isolation region, gate electrodes, insulating film, doping, forming source and drain regions, forming metal silicide films |
| 06/16/1998 | US5766824 Method and apparatus for curing photoresist |
| 06/16/1998 | US5766823 Method of manufacturing semiconductor devices |
| 06/16/1998 | US5766809 Method for testing overlay in a semiconductor device utilizing inclined measuring mark |
| 06/16/1998 | US5766808 Process for forming multilayer lift-off structures |
| 06/16/1998 | US5766806 Simplified production of integrated circuits |
| 06/16/1998 | US5766805 Forming conductive light shielding layer on transparent substrate, implanting oxygen ions, selectively etching to form phase shift film |
| 06/16/1998 | US5766804 Method of optical lithography using phase shift masking |