Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2000
05/17/2000CN1253376A Method for making semi-conductor device
05/17/2000CN1253363A Resistance for regulation and semiconductor equipment and production method thereof
05/17/2000CN1253311A Printing sub photo etching image by using shadow arbor and eccentric shaft exposure
05/17/2000CN1253160A New type abrasive composition used in integrated circuit electronic industry
05/17/2000CN1052576C 半导体器件 Semiconductor devices
05/17/2000CN1052575C Semiconductor device and manufacturing method for same
05/17/2000CN1052574C Electronic device having thin-film transistors
05/17/2000CN1052573C Method of manufacturing semiconductor device
05/17/2000CN1052572C Method for manufacturing semiconductor device
05/17/2000CN1052571C Semiconductor device and method of fabricating same
05/17/2000CN1052570C Semiconductor device and method for fabricating same
05/17/2000CN1052569C Method for fabricating semiconductor device
05/17/2000CN1052568C Method for forming semiconductor device
05/17/2000CN1052567C Semiconductor device and method of fabricating same
05/17/2000CN1052566C Method for processing semiconductor device
05/17/2000CN1052565C Method for manufacturing semiconductor device
05/17/2000CN1052564C Processf or fabricating semiconductor and process for fabricating semiconductor device
05/16/2000US6065143 Semiconductor memory device capable of fast testing without externally considering address scramble or data scramble
05/16/2000US6065142 ROM testing circuit
05/16/2000US6065141 Self-diagnosable semiconductor memory device having a redundant circuit and semiconductor apparatus having the same in which the memory device cannot be accessed from outside the semiconductor apparatus
05/16/2000US6064847 Developing device
05/16/2000US6064807 Charged-particle beam exposure system and method
05/16/2000US6064800 Apparatus for uniform gas and radiant heat dispersion for solid state fabrication processes
05/16/2000US6064799 Method and apparatus for controlling the radial temperature gradient of a wafer while ramping the wafer temperature
05/16/2000US6064621 Multi-bank clock synchronous type semiconductor memory device having improved memory array and power supply arrangement
05/16/2000US6064618 Semiconductor memory device having improved cell array layout
05/16/2000US6064606 Semiconductor integrated circuit device
05/16/2000US6064595 Floating gate memory apparatus and method for selected programming thereof
05/16/2000US6064593 Semiconductor integrated circuit device having an electrically erasable and programmable nonvolatile memory and a built-in processing unit
05/16/2000US6064592 Non-volatile semiconductor memory featuring effective cell area reduction using contactless technology
05/16/2000US6064589 Double gate DRAM memory cell
05/16/2000US6064557 Semiconductor device structured to be less susceptible to power supply noise
05/16/2000US6064556 Protection circuit for an electric pulse supply line in a semiconductor integrated device
05/16/2000US6064484 Pattern inspection method and system
05/16/2000US6064477 Method of and apparatus for inspecting reticle for defects
05/16/2000US6064475 Real time local defocus monitor system using maximum and mean angles of focus correction
05/16/2000US6064467 Alignment apparatus, and exposure apparatus with the alignment apparatus
05/16/2000US6064466 Planarization method and system using variable exposure
05/16/2000US6064456 Process for manufacturing reflection-type liquid crystal display apparatus
05/16/2000US6064256 High frequency multi-stage capacitively coupled amplifier circuits
05/16/2000US6064233 Semiconductor integrated circuit measuring current to test damaged transistor
05/16/2000US6064225 Global signal distribution with reduced routing tracks in an FPGA
05/16/2000US6064221 Method of temporarily securing a die to a burn-in carrier
05/16/2000US6064219 Modular test chip for multi chip module
05/16/2000US6064194 Method and apparatus for automatically positioning electronic dice within component packages
05/16/2000US6064120 Apparatus and method for face-to-face connection of a die face to a substrate with polymer electrodes
05/16/2000US6064119 Wiring structure and formation method thereof for semiconductor device
05/16/2000US6064118 Multilevel interconnection structure having an air gap between interconnects
05/16/2000US6064114 Semiconductor device having a sub-chip-scale package structure and method for forming same
05/16/2000US6064110 Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
05/16/2000US6064109 Ballast resistance for producing varied emitter current flow along the emitter's injecting edge
05/16/2000US6064108 Integrated interdigitated capacitor
05/16/2000US6064107 Gate structure of a semiconductor device having an air gap
05/16/2000US6064106 Bipolar transistor having isolation regions
05/16/2000US6064105 Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide
05/16/2000US6064104 Trench isolation structures with oxidized silicon regions and method for making the same
05/16/2000US6064103 Device with a P-N junction and a means of reducing the risk of breakdown of the junction
05/16/2000US6064102 Semiconductor device having gate electrodes with different gate insulators and fabrication thereof
05/16/2000US6064101 Read-only memory cell arrangement
05/16/2000US6064100 Product for ROM components having a silicon controlled rectifier structure
05/16/2000US6064099 Layout of well contacts and source contacts of a semiconductor device
05/16/2000US6064098 Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry, and memory and other circuitry
05/16/2000US6064097 Wiring layers for a semiconductor integrated circuit device
05/16/2000US6064096 Semiconductor LDD device having halo impurity regions
05/16/2000US6064094 Over-voltage protection system for integrated circuits using the bonding pads and passivation layer
05/16/2000US6064092 Semiconductor-on-insulator substrates containing electrically insulating mesas
05/16/2000US6064091 Thin film transistors having an active region composed of intrinsic and amorphous semiconducting layers
05/16/2000US6064090 Semiconductor device having a portion of gate electrode formed on an insulating substrate
05/16/2000US6064089 Semiconductor device
05/16/2000US6064087 Single feature size MOS technology power device
05/16/2000US6064086 Semiconductor device having lateral IGBT
05/16/2000US6064085 DRAM cell with a multiple fin-shaped structure capacitor
05/16/2000US6064084 Semiconductor device having a reliable contact structure
05/16/2000US6064082 Heterojunction field effect transistor
05/16/2000US6064081 Silicon-germanium-carbon compositions and processes thereof
05/16/2000US6064078 Formation of group III-V nitride films on sapphire substrates with reduced dislocation densities
05/16/2000US6064077 Integrated circuit transistor
05/16/2000US6064075 Field emission displays with reduced light leakage having an extractor covered with a silicide nitride formed at a temperature above 1000° C.
05/16/2000US6063953 Chemical-sensitization photoresist composition
05/16/2000US6063896 Acrylic acid/ester-maleimide derivative copolymer having improved etch and heat resistance; high resolution submicrolithography
05/16/2000US6063828 Curable composition with initiators with maleimides
05/16/2000US6063714 Nanoporous dielectric thin film surface modification
05/16/2000US6063713 Methods for forming silicon nitride layers on silicon-comprising substrates
05/16/2000US6063712 Etchant includes at least one fluorine-containing compound and at least one auxiliary component selected from the group of a boron-containing compound and a phosphorus-containing compound
05/16/2000US6063711 Etch-stop can be made thinner than the conventionally used nitride layer; the disclosed oxynitride etch-stop layer makes it possible to avoid the cracking problems of thicker etch-stop layers
05/16/2000US6063710 Method and apparatus for dry etching with temperature control
05/16/2000US6063709 Removal of SOG etchback residue by argon treatment
05/16/2000US6063708 Method for forming isolation layer in semiconductor device
05/16/2000US6063707 Forming underlayer film of a lower atomic weight over the substrate, which will allow sputtering of a material without significant resputtering, depositing a dielectric layer, depositing an overlayer over said dielectric layer
05/16/2000US6063706 Method to simulataneously fabricate the self-aligned silicided devices and ESD protective devices
05/16/2000US6063704 Process for incorporating silicon oxynitride DARC layer into formation of silicide polysilicon contact
05/16/2000US6063703 Method for making metal interconnection
05/16/2000US6063702 Global planarization method for inter level dielectric layers using IDL blocks
05/16/2000US6063701 Conductive particle transferring method
05/16/2000US6063700 Method of forming ohmic conductive components in a single chamber process
05/16/2000US6063699 Methods for making high-aspect ratio holes in semiconductor and its application to a gate damascene process for sub- 0.05 micron mosfets
05/16/2000US6063698 Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits
05/16/2000US6063697 Crushing of silicon on ultrapure ice
05/16/2000US6063696 Method of reducing wafer particles after partial saw using a superhard protective coating
05/16/2000US6063695 Simplified process for the fabrication of deep clear laser marks using a photoresist mask
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