Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2002
10/01/2002US6459157 Semiconductor device and double-sided multi-chip package
10/01/2002US6459156 Semiconductor device, a process for a semiconductor device, and a process for making a masking database
10/01/2002US6459155 Damascene processing employing low Si-SiON etch stop layer/arc
10/01/2002US6459154 Bonding pad structure of a semiconductor device and method of fabricating the same
10/01/2002US6459153 Compositions for improving interconnect metallization performance in integrated circuits
10/01/2002US6459152 Semiconductor device having a chip, reinforcing plate, and sealing material sharing a common rear surface
10/01/2002US6459150 Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer
10/01/2002US6459149 Electronic component, communication device, and manufacturing method for electronic component
10/01/2002US6459145 Semiconductor device having an improved structure for preventing cracks, and improved small-sized semiconductor
10/01/2002US6459141 Method and apparatus for suppressing the channeling effect in high energy deep well implantation
10/01/2002US6459140 Indium-enhanced bipolar transistor
10/01/2002US6459139 Semiconductor device and method of fabricating the same
10/01/2002US6459138 Capacitor structures
10/01/2002US6459137 Layer of a non-conducting metallic oxide bonded to silicon dioxide substrate; first platinum layer electrode bonded to said metallic oxide; bottom layer of ferroelectric material bonded to first electrode; second electrode
10/01/2002US6459136 Single metal programmability in a customizable integrated circuit device
10/01/2002US6459135 Monolithic integrated circuit incorporating an inductive component and process for fabricating such an integrated circuit
10/01/2002US6459134 Semiconductor devices which have analog and digital circuits integrated on a common substrate
10/01/2002US6459132 Image sensing device and production process thereof
10/01/2002US6459129 BiCMOS device having a CMOS gate electrode and a bipolar emitter each containing two impurities of the same conductivity type
10/01/2002US6459128 Field-effect transistor
10/01/2002US6459126 Semiconductor device including a MIS transistor
10/01/2002US6459125 SOI based transistor inside an insulation layer with conductive bump on the insulation layer
10/01/2002US6459124 Semiconductor device and process for manufacturing the same, and electronic device
10/01/2002US6459123 Double gated transistor
10/01/2002US6459122 Semiconductor device having a U-shaped groove in the body of the device
10/01/2002US6459121 Method for producing non-violatile semiconductor memory device and the device
10/01/2002US6459120 Semiconductor device and manufacturing method of the same
10/01/2002US6459118 NAND type nonvolatile ferroelectric memory cell
10/01/2002US6459117 Integrated circuit device formed with high Q MIM capacitor
10/01/2002US6459116 Capacitor structure
10/01/2002US6459115 Semiconductor memory capacitor with intra-dielectric conductive sidewall spacer
10/01/2002US6459114 Nonvolatile semiconductor memory
10/01/2002US6459113 Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells
10/01/2002US6459112 Semiconductor device and process for fabricating the same
10/01/2002US6459111 Semiconductor device and method for manufacturing the same
10/01/2002US6459110 Semiconductor storage element
10/01/2002US6459106 Dynamic threshold voltage devices with low gate to substrate resistance
10/01/2002US6459105 Apparatus for sawing wafers employing multiple indexing techniques for multiple die dimensions
10/01/2002US6459102 Peripheral structure for monolithic power device
10/01/2002US6459100 Vertical geometry ingan LED
10/01/2002US6459095 Chemically synthesized and assembled electronics devices
10/01/2002US6458907 Organometallic polymerizable monomer acid or ester are useful as resists and are sensitive to imaging irradiation while exhibiting enhanced resistance to reactive ion etching.
10/01/2002US6458723 High temperature implant apparatus
10/01/2002US6458722 Controlled method of silicon-rich oxide deposition using HDP-CVD
10/01/2002US6458721 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers
10/01/2002US6458720 High pressure plasma polymerization of organosilicon compound to polysiloxane in dilute nitrogen gas
10/01/2002US6458719 Low dielectric constant film composed of boron, nitrogen, and hydrogen having thermal resistance, process for forming the film, use of the film between semiconductor device layers, and the device formed from the film
10/01/2002US6458718 Providing a substrate; providing a chemical precursor of the formula (f3c)4-m-nmxmrn, wherein m is silicon or germenium, x is halogen, r is hydrogen or d, activating the precursor to deposit a fluorine containing material onto the substrate
10/01/2002US6458717 Methods of forming ultra-thin buffer oxide layers for gate dielectrics
10/01/2002US6458716 Method of manufacturing a semiconductor device
10/01/2002US6458715 Process of manufacturing semiconductor device
10/01/2002US6458714 Method of selective oxidation in semiconductor manufacture
10/01/2002US6458713 Method for manufacturing semiconductor device
10/01/2002US6458712 Method for regenerating semiconductor wafers
10/01/2002US6458711 Self-aligned silicide process
10/01/2002US6458710 Process for forming uniform multiple contact holes
10/01/2002US6458708 Method for forming metal wiring in semiconductor device
10/01/2002US6458707 Tool for semiconductor manufacturing apparatus and method for using the same
10/01/2002US6458706 Method of forming contact using non-conformal dielectric liner
10/01/2002US6458705 Method for forming via-first dual damascene interconnect structure
10/01/2002US6458704 Light sensitive chemical-mechanical polishing method
10/01/2002US6458703 Method for manufacturing semiconductor devices with allevration of thermal stress generation in conductive coating
10/01/2002US6458702 Methods for making semiconductor chip having both self aligned silicide regions and non-self aligned silicide regions
10/01/2002US6458701 Method for forming metal layer of semiconductor device using metal halide gas
10/01/2002US6458700 Integrated circuitry fabrication method of making a conductive electrical connection
10/01/2002US6458699 Methods of forming a contact to a substrate
10/01/2002US6458698 Controlled-stress stable metallization for electronic and electromechanical devices
10/01/2002US6458697 Semiconductor device and manufacturing method therefor
10/01/2002US6458696 Plated through hole interconnections
10/01/2002US6458695 Methods to form dual metal gates by incorporating metals and their conductive oxides
10/01/2002US6458694 High energy sputtering method for forming interconnects
10/01/2002US6458693 Method of manufacturing a semiconductor device
10/01/2002US6458692 Method of forming contact plug of semiconductor device
10/01/2002US6458691 Dual inlaid process using an imaging layer to protect via from poisoning
10/01/2002US6458690 Method for manufacturing a multilayer interconnection structure
10/01/2002US6458689 Use of PE-SiON or PE-Oxide for contact or via photo and for defect reduction with oxide and w chemical-mechanical polish
10/01/2002US6458688 Semiconductor wafer with improved flatness, and process for producing the semiconductor wafer
10/01/2002US6458687 Method for forming conductive structures
10/01/2002US6458686 Inverse integrated circuit fabrication process
10/01/2002US6458685 Method of forming a self-aligned contact opening
10/01/2002US6458684 Single step process for blanket-selective CVD aluminum deposition
10/01/2002US6458683 Method for forming aluminum bumps by CVD and wet etch
10/01/2002US6458682 Method of manufacturing a bump electrode semiconductor device using photosensitive resin
10/01/2002US6458681 Method for providing void free layer for semiconductor assemblies
10/01/2002US6458680 Method of fabricating contact pads of a semiconductor device
10/01/2002US6458679 Method of making silicide stop layer in a damascene semiconductor structure
10/01/2002US6458678 Transistor formed using a dual metal process for gate and source/drain region
10/01/2002US6458677 Process for fabricating an ONO structure
10/01/2002US6458676 Method of varying the resistance along a conductive layer
10/01/2002US6458675 Semiconductor device having a plasma-processed layer and method of manufacturing the same
10/01/2002US6458674 Process for manufacturing semiconductor integrated circuit device
10/01/2002US6458673 Transparent and conductive zinc oxide film with low growth temperature
10/01/2002US6458672 Controlled cleavage process and resulting device using beta annealing
10/01/2002US6458671 Method of providing a shallow trench in a deep-trench device
10/01/2002US6458669 Method of manufacturing an integrated circuit
10/01/2002US6458668 Method for manufacturing hetero junction bipolar transistor
10/01/2002US6458666 Spot-implant method for MOS transistor applications
10/01/2002US6458665 Halo ion implantation method for fabricating a semiconductor device
10/01/2002US6458664 Forming mask layer on surface of semiconductor substrate, selectively removing region of mask layer forming gate region, forming implantation mask layer on surface of mask layer in region including gate, forming anti-punch-through region
10/01/2002US6458663 Masked nitrogen enhanced gate oxide
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