Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2002
10/08/2002US6461981 Method of forming a conformal oxide film
10/08/2002US6461980 Apparatus and process for controlling the temperature of a substrate in a plasma reactor chamber
10/08/2002US6461979 LPCVD furnace uniformity improvement by temperature ramp down deposition system
10/08/2002US6461978 Method of manufacturing a substrate for an electronic device by using etchant and electronic device having the substrate
10/08/2002US6461977 Method of manufacturing semiconductor device
10/08/2002US6461976 Anisotropic etch method
10/08/2002US6461975 Method of etching insulating layer in semiconductor device
10/08/2002US6461974 High temperature tungsten etching process
10/08/2002US6461973 Method for forming high quality multiple thickness oxide layers by reducing descum induced defects
10/08/2002US6461972 Integrated circuit fabrication dual plasma process with separate introduction of different gases into gas flow
10/08/2002US6461971 Method of residual resist removal after etching of aluminum alloy filmsin chlorine containing plasma
10/08/2002US6461970 Method of reducing defects in anti-reflective coatings and semiconductor structures fabricated thereby
10/08/2002US6461969 Multiple-step plasma etching process for silicon nitride
10/08/2002US6461968 Method for fabricating a semiconductor device
10/08/2002US6461967 Material removal method for forming a structure
10/08/2002US6461966 Method of high density plasma phosphosilicate glass process on pre-metal dielectric application for plasma damage reducing and throughput improvement
10/08/2002US6461964 Methods and apparatuses for monitoring and controlling mechanical or chemical-mechanical planarization of microelectronic substrate assemblies
10/08/2002US6461963 Utilization of disappearing silicon hard mask for fabrication of semiconductor structures
10/08/2002US6461962 Etching silicon dioxide layer formed on workpiece placed inside airtight processing chamber by introducing processing gas containing at least octafluorocyclopentene and methylene fluoride at specified flow rate ratio; etch selectivity
10/08/2002US6461961 Depositing a ruthenium film with excellent homogeneity and film quality, by reacting a ruthenium precursor and oxygen containing gas, controlling oxygen stoichiometry to prevent formation of the ruthenium oxide film
10/08/2002US6461960 Method of manufacturing a semiconductor device
10/08/2002US6461959 Method of fabrication of a contact plug in an embedded memory
10/08/2002US6461957 Method of manufacturing semiconductor device
10/08/2002US6461956 Method of forming package
10/08/2002US6461955 Yield improvement of dual damascene fabrication through oxide filling
10/08/2002US6461954 High speed heating in hydrogen environment
10/08/2002US6461953 Solder bump forming method, electronic component mounting method, and electronic component mounting structure
10/08/2002US6461952 Method for growing barium titanate thin film
10/08/2002US6461951 Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers
10/08/2002US6461950 Semiconductor processing methods, semiconductor circuitry, and gate stacks
10/08/2002US6461949 Method for fabricating a nitride read-only-memory (NROM)
10/08/2002US6461948 Method of doping silicon with phosphorus and growing oxide on silicon in the presence of steam
10/08/2002US6461947 Photovoltaic device and making of the same
10/08/2002US6461946 Method of manufacturing semiconductor device
10/08/2002US6461945 Solid phase epitaxy process for manufacturing transistors having silicon/germanium channel regions
10/08/2002US6461944 Methods for growth of relatively large step-free SiC crystal surfaces
10/08/2002US6461943 Method of making semiconductor device
10/08/2002US6461942 Semiconductor chip removing and conveying method and device
10/08/2002US6461941 Method of forming capacitor on cell region including forming dummy pattern around alignment key
10/08/2002US6461940 Dicing blade and method of producing an electronic component
10/08/2002US6461939 SOI wafers and methods for producing SOI wafer
10/08/2002US6461938 Wafer sheet comprising an expandable resin sheet with thermosetting adhesive layers formed on both sides thereof, whereon a semiconductor wafer is attached on the back side thereof before dicing
10/08/2002US6461937 Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching
10/08/2002US6461936 Double pullback method of filling an isolation trench
10/08/2002US6461935 Method of manufacturing trench-shaped isolator
10/08/2002US6461934 Method of manufacturing semiconductor device having trench type element isolation regions
10/08/2002US6461933 SPIMOX/SIMOX combination with ITOX option
10/08/2002US6461932 Semiconductor trench isolation process that utilizes smoothening layer
10/08/2002US6461931 Thin dielectric films for DRAM storage capacitors
10/08/2002US6461930 First electrode formed on the layer of insulating material having a nodular shape, layer of a dielectric material formed on the first electrode and a second electrode formed on the layer of the dielectric material
10/08/2002US6461929 Method for the fine tuning of a passive electronic component
10/08/2002US6461928 Methodology for high-performance, high reliability input/output devices and analog-compatible input/output and core devices using core device implants
10/08/2002US6461927 Semiconductor device and method of producing the same
10/08/2002US6461925 Method of manufacturing a heterojunction BiCMOS integrated circuit
10/08/2002US6461924 MOS transistor for high-speed and high-performance operation and manufacturing method thereof
10/08/2002US6461923 Sidewall spacer etch process for improved silicide formation
10/08/2002US6461922 Method for the integration of resistors and esd self-protected transistors in an integrated device with a memory matrix manufactured by means of a process featuring self-aligned source (sas) formation and junction salicidation
10/08/2002US6461921 Semiconductor device having channel stopper portions integrally formed as part of a well
10/08/2002US6461920 Semiconductor device and method of manufacturing the same
10/08/2002US6461919 Method for fabricating semiconductor device with different gate oxide compositions
10/08/2002US6461917 Memory device, manufacturing method thereof and integrated circuit thereof
10/08/2002US6461916 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making the device
10/08/2002US6461915 Method and structure for an improved floating gate memory cell
10/08/2002US6461914 Process for making a MIM capacitor
10/08/2002US6461913 Semiconductor memory device having plug contacted to a capacitor electrode and method for fabricating a capacitor of the semiconductor memory device
10/08/2002US6461912 Method of fabricating semiconductor storage device having a capacitor
10/08/2002US6461911 Semiconductor memory device and fabricating method thereof
10/08/2002US6461910 Method of forming a capacitor in a semiconductor device
10/08/2002US6461909 Process for fabricating RuSixOy-containing adhesion layers
10/08/2002US6461908 Method of manufacturing a semiconductor device
10/08/2002US6461907 Semiconductor device and fabrication method
10/08/2002US6461906 Method for forming memory cell by using a dummy polysilicon layer
10/08/2002US6461905 Dummy gate process to reduce the Vss resistance of flash products
10/08/2002US6461904 Structure and method for making a notched transistor with spacers
10/08/2002US6461903 Method for fabricating a part depletion type SOI device preventing a floating body effect
10/08/2002US6461902 RF LDMOS on partial SOI substrate
10/08/2002US6461901 Method of forming a thin-film transistor having a high resistance back channel region
10/08/2002US6461900 Method to form a self-aligned CMOS inverter using vertical device integration
10/08/2002US6461899 Oxynitride laminate “blocking layer” for thin film semiconductor devices
10/08/2002US6461898 Two step wire bond process
10/08/2002US6461896 Process for mounting electronic device and semiconductor device
10/08/2002US6461894 Methods of forming a circuit and methods of preparing an integrated circuit
10/08/2002US6461892 Methods of making a connection component using a removable layer
10/08/2002US6461891 Method of constructing an electronic assembly having an indium thermal couple and an electronic assembly having an indium thermal couple
10/08/2002US6461890 Structure of semiconductor chip suitable for chip-on-board system and methods of fabricating and mounting the same
10/08/2002US6461889 Method of fabricating semiconductor device with diamond substrate
10/08/2002US6461887 Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth
10/08/2002US6461886 Method of manufacturing a semiconductor device
10/08/2002US6461885 Method of fabricating and structure of an active matrix light-emitting display device
10/08/2002US6461882 Fault simulation method and fault simulator for semiconductor integrated circuit
10/08/2002US6461881 Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures
10/08/2002US6461880 Method for monitoring silicide failures
10/08/2002US6461879 Method and apparatus for measuring effects of packaging stresses of common IC electrical performance parameters at wafer sort
10/08/2002US6461878 Feedback control of strip time to reduce post strip critical dimension variation in a transistor gate electrode
10/08/2002US6461877 Variable data compensation for vias or contacts
10/08/2002US6461801 Rapid heating and cooling of workpiece chucks
10/08/2002US6461800 Resist patterning method
10/08/2002US6461796 Forming on substrate resist mask having opening with tapered side wall, forming water soluble resist film on mask to cover taper, allowing film to react with acid to form water insoluble portion, removing water soluble film, doping
10/08/2002US6461785 Composition for positive photoresist
10/08/2002US6461738 Heat and solvent resistance
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