Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2003
07/08/2003US6590238 Image sensor having a capacitance control gate for improved gain control and eliminating undesired capacitance
07/08/2003US6590237 Layout structure for dynamic random access memory
07/08/2003US6590236 Semiconductor structure for use with high-frequency signals
07/08/2003US6590231 Transistor that uses carbon nanotube ring
07/08/2003US6590230 Semiconductor device and manufacturing method thereof
07/08/2003US6590229 Semiconductor device and process for production thereof
07/08/2003US6590228 LCD device with optimized channel characteristics
07/08/2003US6590227 Active matrix display device
07/08/2003US6590226 Thin film transistor array substrate, method for manufacturing the same and system for inspecting the substrate
07/08/2003US6590219 Apparatus and method for forming photoresist pattern with target critical dimension
07/08/2003US6590218 Projection-exposure methods and apparatus exhibiting increased throughput
07/08/2003US6590216 Servo control for high emittance electron source
07/08/2003US6590186 Heat treatment apparatus and method
07/08/2003US6590182 Laser repair apparatus and method
07/08/2003US6590181 Laser cutter apparatus using two laser beams of different wavelengths
07/08/2003US6590179 Plasma processing apparatus and method
07/08/2003US6590165 Printed wiring board having throughole and annular lands
07/08/2003US6590010 Organosiloxane polymer, photo-curable resin composition, patterning process, and substrate protective coating
07/08/2003US6589890 Precleaning process for metal plug that minimizes damage to low-κ dielectric
07/08/2003US6589889 Contact planarization using nanoporous silica materials
07/08/2003US6589888 Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers
07/08/2003US6589887 Forming metal-derived layers by simultaneous deposition and evaporation of metal
07/08/2003US6589886 Method for manufacturing aluminum oxide film for use in a semiconductor device
07/08/2003US6589885 Semiconductor device and method in which contact hole is filled with silicon having low impurity concentration
07/08/2003US6589884 Method of forming an inset in a tungsten silicide layer in a transistor gate stack
07/08/2003US6589883 Enhancement, stabilization and metallization of porous silicon
07/08/2003US6589882 Copper post-etch cleaning process
07/08/2003US6589881 Method of forming dual damascene structure
07/08/2003US6589880 Fine pattern formation method and semiconductor device or liquid crystal device manufacturing method employing this method
07/08/2003US6589879 Nitride open etch process based on trifluoromethane and sulfur hexafluoride
07/08/2003US6589878 Method of cleaning a wafer in an IC fabrication
07/08/2003US6589877 Method of providing an oxide
07/08/2003US6589876 Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays
07/08/2003US6589875 Method of selectively processing wafer edge regions to increase wafer uniformity, and system for accomplishing same
07/08/2003US6589874 Method for forming electromigration-resistant structures by doping
07/08/2003US6589873 Process for manufacturing a semiconductor device
07/08/2003US6589871 Processing method, measuring method and producing method of semiconductor devices
07/08/2003US6589869 Film thickness control using spectral interferometry
07/08/2003US6589868 Si seasoning to reduce particles, extend clean frequency, block mobile ions and increase chamber throughput
07/08/2003US6589867 Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug
07/08/2003US6589866 Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process
07/08/2003US6589865 Low pressure, low temperature, semiconductor gap filling process
07/08/2003US6589864 Method for defining windows with different etching depths simultaneously
07/08/2003US6589863 Semiconductor device and manufacturing method thereof
07/08/2003US6589862 Lower layer comprises a non-silicon containing organic polymer and an upper layer comprises an organic, silicon containing polymer
07/08/2003US6589861 Method for fabricating a semiconductor device
07/08/2003US6589860 System and method for calibrating electron beam defect inspection tool
07/08/2003US6589859 Method of manufacturing an electronic power component, and an electronic power component obtained thereby
07/08/2003US6589858 Method of making metal gate stack with etch endpoint tracer layer
07/08/2003US6589857 Manufacturing method of semiconductor film
07/08/2003US6589856 Method and apparatus for controlling anti-phase domains in semiconductor structures and devices
07/08/2003US6589855 Methods of processing semiconductor wafer and producing IC card, and carrier
07/08/2003US6589854 Method of forming shallow trench isolation
07/08/2003US6589853 Method of forming a trench isolation structure having a second nitride film
07/08/2003US6589851 Semiconductor processing methods of forming a conductive grid
07/08/2003US6589850 Method and system for fabricating a bipolar transistor and related structure
07/08/2003US6589849 Method for fabricating epitaxy base bipolar transistor
07/08/2003US6589848 Photodetector device and method for manufacturing the same
07/08/2003US6589847 Tilted counter-doped implant to sharpen halo profile
07/08/2003US6589846 Method for fabricating semiconductor device including self aligned gate
07/08/2003US6589844 Process for manufacturing semiconductor memory device having floating and control gates in which multiple insulating films are formed over floating gates
07/08/2003US6589843 Methods of forming FLASH field effect transistor gates and non-FLASH field effect transistor gates
07/08/2003US6589842 Manufacturing method of a gate-split flash memory
07/08/2003US6589841 Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate
07/08/2003US6589840 Nonvolatile memory device with reduced floating gate and increased coupling ratio and manufacturing method thereof
07/08/2003US6589839 Dielectric cure for reducing oxygen vacancies
07/08/2003US6589838 Capacitor and conductive line constructions and semiconductor processing methods of forming capacitors and conductive lines
07/08/2003US6589837 Buried contact structure in semiconductor device and method of making the same
07/08/2003US6589836 One step dual salicide formation for ultra shallow junction applications
07/08/2003US6589835 Method of manufacturing flash memory
07/08/2003US6589834 Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current
07/08/2003US6589833 ESD parasitic bipolar transistors with high resistivity regions in the collector
07/08/2003US6589832 Spacer formation in a deep trench memory cell
07/08/2003US6589831 Transistor structure using epitaxial layers and manufacturing method thereof
07/08/2003US6589830 Self-aligned process for fabricating power MOSFET with spacer-shaped terraced gate
07/08/2003US6589829 Semiconductor device and method for forming the same
07/08/2003US6589828 Fabricating a thin film transistor having better punch through resistance and hot carrier effects
07/08/2003US6589827 Semiconductor device and method for fabricating the same
07/08/2003US6589826 Thin film transistor and a method of forming the same
07/08/2003US6589825 Method for re-forming semiconductor layer in TFT-LCD
07/08/2003US6589824 Process for fabricating semiconductor device
07/08/2003US6589823 Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug
07/08/2003US6589822 Manufacturing method for top-gate type and bottom-gate type thin film transistors
07/08/2003US6589821 Methods of forming thin film transistors
07/08/2003US6589820 Method and apparatus for packaging a microelectronic die
07/08/2003US6589819 Microelectronic packages having an array of resilient leads and methods therefor
07/08/2003US6589818 Method for mounting a thin semiconductor device
07/08/2003US6589817 Semiconductor device, method for manufacturing the same, and method for mounting the same
07/08/2003US6589816 Method of forming metal connection elements in integrated circuits
07/08/2003US6589815 Method of manufacturing semiconductor device with plated heat sink by laser cutting
07/08/2003US6589814 Lead frame chip scale package
07/08/2003US6589813 Chip size stack package and method of fabricating the same
07/08/2003US6589811 Method for transferring semiconductor device layers to different substrates
07/08/2003US6589810 BGA package and method of fabrication
07/08/2003US6589809 Method for attaching semiconductor components to a substrate using local UV curing of dicing tape
07/08/2003US6589802 Packaging structure and method of packaging electronic parts
07/08/2003US6589801 Wafer-scale production of chip-scale semiconductor packages using wafer mapping techniques
07/08/2003US6589719 Photoresist stripper compositions
07/08/2003US6589718 Forming a resist layer on a target layer and patterning the resist layer to form original openings and a slit in the resist layer, reflowing resist layer patterned under heat to cause deformation of original openings and the slit
07/08/2003US6589715 The plasma polymerized organosilicon film having an upper stratum overlying a lower stratum wherein the upper stratum is more photosensitive to ultraviolet radiation than is the lower stratum
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