Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2003
07/01/2003US6586340 Wafer processing apparatus and wafer processing method using the same
07/01/2003US6586339 Silicon barrier layer to prevent resist poisoning
07/01/2003US6586338 Methods for creating elements of predetermined shape and apparatus using these elements
07/01/2003US6586336 Chemical-mechanical-polishing station
07/01/2003US6586335 Thin film transistor and method of manufacturing the same
07/01/2003US6586334 Reducing copper line resistivity by smoothing trench and via sidewalls
07/01/2003US6586333 Integrated plasma treatment and nickel deposition and tool for performing same
07/01/2003US6586332 Deep submicron silicide blocking
07/01/2003US6586331 Low sheet resistance of titanium salicide process
07/01/2003US6586330 Method for depositing conformal nitrified tantalum silicide films by thermal CVD
07/01/2003US6586329 Semiconductor device and a method of manufacturing thereof
07/01/2003US6586328 Method to metallize ohmic electrodes to P-type group III nitrides
07/01/2003US6586327 Fabrication of semiconductor devices
07/01/2003US6586326 Metal planarization system
07/01/2003US6586325 Process for making an electronic device having a multilevel structure
07/01/2003US6586324 Method of forming interconnects
07/01/2003US6586323 Method for dual-layer polyimide processing on bumping technology
07/01/2003US6586322 Method of making a bump on a substrate using multiple photoresist layers
07/01/2003US6586321 Method for forming metal silicide layer
07/01/2003US6586320 Graded/stepped silicide process to improve mos transistor
07/01/2003US6586319 High-speed compound semiconductor device having a minimized parasitic capacitance and resistance
07/01/2003US6586318 Thin phosphorus nitride film as an N-type doping source used in laser doping technology
07/01/2003US6586317 Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage
07/01/2003US6586316 Method for producing a semiconductor substrate
07/01/2003US6586314 Method of forming shallow trench isolation regions with improved corner rounding
07/01/2003US6586313 Method of avoiding the effects of lack of uniformity in trench isolated integrated circuits
07/01/2003US6586312 Method for fabricating a DRAM capacitor and device made
07/01/2003US6586311 Salicide block for silicon-on-insulator (SOI) applications
07/01/2003US6586310 High resistivity film for 4T SRAM
07/01/2003US6586308 Method for producing circuit structures on a semiconductor substrate and semiconductor configuration with functional circuit structures and dummy circuit structures
07/01/2003US6586307 Method for controlling an emitter window opening in an HBT and related structure
07/01/2003US6586306 Method for fabricating semiconductor device
07/01/2003US6586305 Method for producing transistors in integrated semiconductor circuits
07/01/2003US6586304 Semiconductor-on-insulator transistor, memory circuitry employing semiconductor-on-insulator transistors, method of forming a semiconductor-on-insulator transistor, and method of forming memory circuitry employing semiconductor-on-insulator transistors
07/01/2003US6586303 Method for fabricating a mask ROM
07/01/2003US6586302 Method of using trenching techniques to make a transistor with a floating gate
07/01/2003US6586301 Method of fabricating EEPROM having tunnel window area
07/01/2003US6586300 Spacer assisted trench top isolation for vertical DRAM's
07/01/2003US6586299 Mixed mode process
07/01/2003US6586298 Method of forming high performance bipolar transistor
07/01/2003US6586297 Method for integrating a metastable base into a high-performance HBT and related structure
07/01/2003US6586296 Method of doping wells, channels, and gates of dual gate CMOS technology with reduced number of masks
07/01/2003US6586295 Semiconductor device manufacturing method and semiconductor device
07/01/2003US6586294 Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks
07/01/2003US6586293 Semiconductor device and method of manufacturing the same
07/01/2003US6586291 High density memory with storage capacitor
07/01/2003US6586290 Structure for ESD protection in semiconductor chips
07/01/2003US6586289 Anti-spacer structure for improved gate activation
07/01/2003US6586288 Method of forming dual-metal gates in semiconductor device
07/01/2003US6586287 Method for fabricating thin film transistor including crystalline silicon active layer
07/01/2003US6586286 Method for fabricating thin film transistor array substrate for liquid crystal display
07/01/2003US6586284 Silicon-on-insulator (SOI) substrate, method for fabricating SOI substrate and SOI MOSFET using the SOI substrate
07/01/2003US6586283 Apparatus and method for protecting integrated circuit charge storage elements from photo-induced currents
07/01/2003US6586282 Method of manufacturing a semiconductor device
07/01/2003US6586281 Variable rotational assignment of interconnect levels in integrated circuit fabrication
07/01/2003US6586280 Method of manufacturing a semiconductor chip array with two-sided cooling
07/01/2003US6586279 Method of integrating a heat spreader and a semiconductor, and package formed thereby
07/01/2003US6586278 Method for mounting electronic component and structure having mounted thereon an electronic component
07/01/2003US6586277 Method and structure for manufacturing improved yield semiconductor packaged devices
07/01/2003US6586275 Wafer level package and method for manufacturing the same
07/01/2003US6586273 Semiconductor device manufacturing method having a step of applying a copper foil on a substrate as a part of a wiring connecting an electrode pad to a mounting terminal
07/01/2003US6586272 Method for manufacturing MSM photodetector or using a HEMT structure incorporating a low-temperature grown semiconductor
07/01/2003US6586270 Process for producing a photovoltaic element
07/01/2003US6586266 High performance sub-system design and assembly
07/01/2003US6586265 Method and apparatus of tool matching for a semiconductor manufacturing process
07/01/2003US6586264 Method of calculating characteristics of semiconductor device having gate electrode and program thereof
07/01/2003US6586263 Correction of overlay offset between inspection layers in integrated circuits
07/01/2003US6586262 Etching end-point detecting method
07/01/2003US6586261 Method for determining a preceding wafer group
07/01/2003US6586260 Integrated circuits
07/01/2003US6586168 Exposure method based on multiple exposure process
07/01/2003US6586163 Method of forming fine pattern
07/01/2003US6586162 Protective coating for silicon nitride spacer
07/01/2003US6586161 For prevention of contamination of wafers, made of transition metal (platinum, ruthenium, copper, and perovskite) thin film wherein the edges are removed via orthoperiodic acid and nitric acid, then lithography
07/01/2003US6586154 Photoresist polymer of following formula 1, and a photoresist composition comprising photoresist composition has excellent transparency in deep ultraviolet region, etching resistance and heat resistance, and can form a good pattern without
07/01/2003US6586153 Multilayer devices formed by multilayer thermal transfer
07/01/2003US6586145 Method of fabricating semiconductor device and semiconductor device
07/01/2003US6586144 Lithography; screen printing, curing
07/01/2003US6586143 Chemical mechanical polishing (CMP) process and automatically compensating for alignment of a wafer stepper based on the position checking is described. A wafer is provided having an alignment mark thereon for the purpose of aligning a reticle
07/01/2003US6586113 Interfaces and etched heterojunction structures are described. A bottom layer is deposited on a substrate, a transition etch layer is deposited over the bottom layer, and a top layer is deposited over the transition etch layer.
07/01/2003US6586068 Ideal oxygen precipitating silicon wafer having an asymmetrical vacancy concentration profile and a process for the preparation thereof
07/01/2003US6586043 Methods of electroless deposition of nickel, methods of forming under bump metallurgy, and constructions comprising solder bumps
07/01/2003US6585925 Process for forming molded heat dissipation devices
07/01/2003US6585910 Etchant
07/01/2003US6585908 Shallow angle interference process and apparatus for determining real-time etching rate
07/01/2003US6585907 Method for manufacturing a shield for an inductively-couple plasma apparatus
07/01/2003US6585905 Leadless plastic chip carrier with partial etch die attach pad
07/01/2003US6585876 Electrolyte cell configured to receive a substrate to have a metal film deposited thereon; a porous, rigid diffuser positioned between where the substrate is to be and the anode; uniform coating; pressure removes bubbles
07/01/2003US6585853 Bonding apparatus
07/01/2003US6585850 Retaining ring with a three-layer structure
07/01/2003US6585828 Process chamber lid service system
07/01/2003US6585826 Semiconductor wafer cleaning method to remove residual contamination including metal nitride particles
07/01/2003US6585825 Metal ion free solution containing base, silicate, stabilizer and water; removing photoresist residues and other metallic and organic contaminates from semiconductor wafers without damaging
07/01/2003US6585823 Atomic layer deposition
07/01/2003US6585821 Measuring absorption to determine reaction completion and terminating heating of lead acetate and diethylene glycol ethyl ether solution; lead di(ethylene glycol)ethyl ether precursor for lead germanium oxide (PGO) production
07/01/2003US6585811 For forming conductive patterns connecting active or passive devices as well as integrated circuits
07/01/2003US6585786 Slurry for chemical mechanical polishing
07/01/2003US6585579 Chemical mechanical planarization or polishing pad with sections having varied groove patterns
07/01/2003US6585572 Subaperture chemical mechanical polishing system
07/01/2003US6585568 Chemical mechanical polishing slurry
1 ... 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 ... 6590