Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2003
08/26/2003US6611061 Tantalum-aluminum-nitrogen material for semiconductor devices
08/26/2003US6611060 Semiconductor device having a damascene type wiring layer
08/26/2003US6611059 Integrated circuitry conductive lines
08/26/2003US6611053 Protective structure for bond wires
08/26/2003US6611049 Semiconductor device with chamfered substrate and method of making the same
08/26/2003US6611048 Exposed paddle leadframe for semiconductor die packaging
08/26/2003US6611047 Semiconductor package with singulation crease
08/26/2003US6611045 Method of forming an integrated circuit device using dummy features and structure thereof
08/26/2003US6611044 Lateral bipolar transistor and method of making same
08/26/2003US6611043 Bipolar transistor and semiconductor device having the same
08/26/2003US6611042 Semiconductor device including resistors isolated and equdistant from diffusion regions
08/26/2003US6611041 Inductor with patterned ground shield
08/26/2003US6611039 Vertically oriented nano-fuse and nano-resistor circuit elements
08/26/2003US6611038 Semiconductor wafer isolation structure formed by field oxidation
08/26/2003US6611037 Multi-trench region for accumulation of photo-generated charge in a CMOS imager
08/26/2003US6611034 Magnetic device and solid-state magnetic memory
08/26/2003US6611033 Micromachined electromechanical (MEM) random access memory array and method of making same
08/26/2003US6611032 Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures
08/26/2003US6611031 Suppressing interband tunneling in transistors; reduced current leakage
08/26/2003US6611030 Cmosfet with conductive, grounded backside connected to the wiring layer through a hole that separates the Mosfets
08/26/2003US6611029 Double gate semiconductor device having separate gates
08/26/2003US6611027 Protection transistor with improved edge structure
08/26/2003US6611026 Substrate-biased silicon diode for electrostatic discharge protection and fabrication method
08/26/2003US6611024 Method of forming PID protection diode for SOI wafer
08/26/2003US6611023 Field effect transistor with self alligned double gate and method of forming same
08/26/2003US6611022 Semiconductor thin film and its manufacturing method and semiconductor device and its manufacturing method
08/26/2003US6611021 Semiconductor device and the method of manufacturing the same
08/26/2003US6611020 Memory cell structure
08/26/2003US6611019 Method and structure for an improved floating gate memory cell
08/26/2003US6611018 Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry
08/26/2003US6611017 Semiconductor device provided with capacitor having cavity-provided electrode
08/26/2003US6611016 Capacitor for semiconductor device and method for manufacturing the same
08/26/2003US6611015 Semiconductor device including dummy upper electrode
08/26/2003US6611014 Semiconductor device having ferroelectric capacitor and hydrogen barrier film and manufacturing method thereof
08/26/2003US6611011 Memory cell array divided into a plurality of subarrays arranged in matrix form
08/26/2003US6611010 Semiconductor device
08/26/2003US6611009 Cross-coupled transistor pair
08/26/2003US6611008 Preventing hole injection from base into emitter layer
08/26/2003US6611007 Method for locally modifying the effective bandgap energy in indium gallium arsenide phosphide (InGaAsP) quantum well structures
08/26/2003US6611006 Vertical component peripheral structure
08/26/2003US6611005 Method for producing semiconductor and semiconductor laser device
08/26/2003US6611002 Smaller; vertically conducting even when nonconducting layer is included
08/26/2003US6610998 Having microlens for focusing electromagnetic waves; reliable, reproducible thin film transistors
08/26/2003US6610996 Semiconductor device using a semiconductor film having substantially no grain boundary
08/26/2003US6610995 Gallium nitride-based III-V group compound semiconductor
08/26/2003US6610993 Load port door assembly with integrated wafer mapper
08/26/2003US6610991 Electronics assembly apparatus with stereo vision linescan sensor
08/26/2003US6610988 Charged particle beam drawing apparatus and charged particle beam drawing method
08/26/2003US6610987 Apparatus and method of ion beam processing
08/26/2003US6610980 Apparatus for inspection of semiconductor wafers and masks using a low energy electron microscope with two illuminating beams
08/26/2003US6610968 System and method for controlling movement of a workpiece in a thermal processing system
08/26/2003US6610967 Utilizing refracted light energy; uniformity
08/26/2003US6610934 Semiconductor module and method of making the device
08/26/2003US6610930 Composite noble metal wire
08/26/2003US6610918 Noncontact; detects short circuit defects; does not require bonding pads
08/26/2003US6610773 Mica, flaked glass, conductive filler consisting of carbon fiber; computer chip tray
08/26/2003US6610616 Method for forming micro-pattern of semiconductor device
08/26/2003US6610615 Plasma nitridation for reduced leakage gate dielectric layers
08/26/2003US6610614 Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates
08/26/2003US6610613 Method for fabricating thin insulating films, a semiconductor device and a method for fabricating a semiconductor device
08/26/2003US6610610 Methods for selective removal of material from wafer alignment marks
08/26/2003US6610609 Compatibilization treatment
08/26/2003US6610608 Plasma etching using combination of CHF3 and CH3F
08/26/2003US6610607 Method to define and tailor process limited lithographic features using a modified hard mask process
08/26/2003US6610606 Method for manufacturing nitride compound based semiconductor device using an RIE to clean a GaN-based layer
08/26/2003US6610604 Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask
08/26/2003US6610603 Method of manufacturing a capacitor
08/26/2003US6610601 Bond pad and wire bond
08/26/2003US6610600 Damascene copper electroplating process with low-pressure pre-processing
08/26/2003US6610599 Removal of metal veils from via holes
08/26/2003US6610597 Method of fabricating a semiconductor device
08/26/2003US6610596 Method of forming metal interconnection using plating and semiconductor device manufactured by the method
08/26/2003US6610595 Ball limiting metallurgy for input/outputs and methods of fabrication
08/26/2003US6610594 Locally increasing sidewall density by ion implantation
08/26/2003US6610593 By decomposing into gaseous products a sacrificial material selected from polycarbonate polymers, polyester polymers, polyether polymers, (meth)acrylate polymers, or blends
08/26/2003US6610592 Method for integrating low-K materials in semiconductor fabrication
08/26/2003US6610591 Methods of ball grid array
08/26/2003US6610590 Method of manufacturing a laser impression on a low thermal conductivity layer of a semiconductor device
08/26/2003US6610587 Method of forming a local interconnect
08/26/2003US6610586 Method for fabricating nitride read-only memory
08/26/2003US6610585 Method for forming a retrograde implant
08/26/2003US6610583 Method for manufacturing semiconductor thin film, and magnetoelectric conversion element provided with semiconductor thin film thereby manufactured
08/26/2003US6610582 Field-assisted fusion bonding
08/26/2003US6610581 Method of forming isolation film in semiconductor device
08/26/2003US6610580 Flash memory array and a method and system of fabrication thereof
08/26/2003US6610579 Semiconductor device having a high-dielectric capacitor
08/26/2003US6610578 Methods of manufacturing bipolar transistors for use at radio frequencies
08/26/2003US6610577 Self-aligned polysilicon polish
08/26/2003US6610576 Method for forming asymmetric dual gate transistor
08/26/2003US6610575 Forming dual gate oxide thickness on vertical transistors by ion implantation
08/26/2003US6610574 Process for forming MOSgated device with trench structure and remote contact
08/26/2003US6610573 Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate
08/26/2003US6610572 Semiconductor device and method for manufacturing the same
08/26/2003US6610571 Approach to prevent spacer undercut by low temperature nitridation
08/26/2003US6610570 Double-bit non-volatile memory structure and corresponding method of manufacture
08/26/2003US6610569 Semiconductor device and process of producing the same
08/26/2003US6610568 Process for fabricating RuSixOy-containing adhesion layers
08/26/2003US6610567 DRAM having a guard ring and process of fabricating the same
08/26/2003US6610566 Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
08/26/2003US6610565 Method of forming a CMOS type semiconductor device
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