Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2003
09/02/2003US6614254 Method for testing semiconductor integrated circuit device equipped with power make-up circuit used in burn-in test
09/02/2003US6614251 Electromigration evaluation circuit
09/02/2003US6614249 Methods of forming apparatuses and a method of engaging electrically conductive test pads on a semiconductor substrate
09/02/2003US6614246 Probe structure
09/02/2003US6614245 Probe for bumps between printed wiring board and circuit component
09/02/2003US6614244 Semiconductor device inspecting apparatus
09/02/2003US6614243 Measurement probe for detecting electrical signals in an integrated semiconductor circuit
09/02/2003US6614235 Apparatus and method for detection and measurement of environmental parameters
09/02/2003US6614201 Substrate transfer system
09/02/2003US6614190 Ion implanter
09/02/2003US6614122 Controlling underfill flow locations on high density packages using physical trenches and dams
09/02/2003US6614120 Semiconductor device
09/02/2003US6614119 Semiconductor device and method of fabricating the same
09/02/2003US6614117 Method for metallization of a semiconductor substrate and related structure
09/02/2003US6614116 Buried digit line stack and process for making same
09/02/2003US6614115 Enhancement of carrier concentration in As-containing layers
09/02/2003US6614114 Conductive line formed on integrated circuits
09/02/2003US6614113 Semiconductor device and method for producing the same
09/02/2003US6614112 Semiconductor device with shock absorbing bond pad
09/02/2003US6614111 Semiconductor device using bumps, method for fabricating same, and method for forming bumps
09/02/2003US6614110 Module with bumps for connection and support
09/02/2003US6614099 Copper metallurgy in integrated circuits
09/02/2003US6614098 Semiconductor devices and fabrication thereof
09/02/2003US6614096 Method for manufacturing a semiconductor device and a semiconductor device
09/02/2003US6614095 Diamond component with rear side contact and a method for the production thereof
09/02/2003US6614094 High integration density vertical capacitor structure and fabrication process
09/02/2003US6614093 Integrated inductor in semiconductor manufacturing
09/02/2003US6614092 Microelectronic device package with conductive elements and associated method of manufacture
09/02/2003US6614091 Semiconductor device having a wire bond pad and method therefor
09/02/2003US6614090 Compensation semiconductor component and method of fabricating the semiconductor component
09/02/2003US6614089 Field effect transistor
09/02/2003US6614088 Breakdown improvement method and sturcture for lateral DMOS device
09/02/2003US6614087 Semiconductor device
09/02/2003US6614085 Metal silicon nitride, photoresist patterning
09/02/2003US6614083 Wiring material and a semiconductor device having wiring using the material, and the manufacturing method
09/02/2003US6614082 Fabrication of semiconductor devices with transition metal boride films as diffusion barriers
09/02/2003US6614081 High-performance MOS transistor of LDD structure having a gate insulating film with a nitride central portion and oxide end portions
09/02/2003US6614080 Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication
09/02/2003US6614079 All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS
09/02/2003US6614078 Highly latchup-immune CMOS I/O structures
09/02/2003US6614077 Semiconductor device improved in ESD reliability
09/02/2003US6614076 EL display device having a pixel portion and a driver circuit
09/02/2003US6614075 Semiconductor device and method of manufacturing the same
09/02/2003US6614074 Grooved planar DRAM transfer device using buried pocket
09/02/2003US6614073 Semiconductor chip with a base electrode and an emitter electrode exposed on one of a pair of opposite lateral faces and a collector electrode exposed on a remaining one of the pair of the opposite lateral faces
09/02/2003US6614072 High coupling split-gate transistor
09/02/2003US6614071 Non-volatile semiconductor memory device
09/02/2003US6614069 Nonvolatile semiconductor memory cell and method for fabricating the memory cell
09/02/2003US6614068 SOI device with reversed stacked capacitor cell and body contact structure and method for fabricating the same
09/02/2003US6614067 Design and process for a dual gate structure
09/02/2003US6614066 Ferroelectric transistor and memory cell configuration with the ferroelectric transistor
09/02/2003US6614065 Use of membrane properties to reduce residual stress in an interlayer region
09/02/2003US6614064 Transistor having a gate stick comprised of a metal, and a method of making same
09/02/2003US6614063 Polypyrrole and/ or polythiophene
09/02/2003US6614062 Semiconductor tiling structure and method of formation
09/02/2003US6614061 Electrostatic discharge-protection semiconductor device
09/02/2003US6614054 Polysilicon thin film transistor used in a liquid crystal display and the fabricating method
09/02/2003US6614053 Active matrix substrate, electrooptical device, and method of producing active matrix substrate
09/02/2003US6614052 Semiconductor display devices and applications
09/02/2003US6614050 Semiconductor manufacturing apparatus
09/02/2003US6614049 System LSI chip having a logic part and a memory part
09/02/2003US6614034 Charged-particle-beam microlithography apparatus and methods including shielding of the beam from extraneous magnetic fields
09/02/2003US6614027 Method of controlling electrostatic lens and ion implantation apparatus
09/02/2003US6614005 Device and method for thermally treating substrates
09/02/2003US6613834 Film forming material comprising siloxane resin and polycarbosilane dissolved together, having relative dielectric constant in range from about 2.5 to 3.0
09/02/2003US6613829 Conductive hardening resin for a semiconductor device and semiconductor device using the same
09/02/2003US6613702 Methods of forming capacitor constructions
09/02/2003US6613700 Method for spin coating high viscosity materials on silicon wafers
09/02/2003US6613699 Process for producing a semiconductor device
09/02/2003US6613698 Lower temperature method for forming high quality silicon-nitrogen dielectrics
09/02/2003US6613697 Low metallic impurity SiO based thin film dielectrics on semiconductor substrates using a room temperature wet chemical growth process, method and applications thereof
09/02/2003US6613696 Method of forming composite silicon oxide layer over a semiconductor device
09/02/2003US6613695 Surface preparation prior to deposition
09/02/2003US6613694 Semiconductor device, manufacturing method for semiconductor device and mounting method for the same
09/02/2003US6613693 Etchant used in the manufacture of semiconductor devices and etching method using the same
09/02/2003US6613692 Substrate processing method and apparatus
09/02/2003US6613691 Highly selective oxide etch process using hexafluorobutadiene
09/02/2003US6613690 Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers
09/02/2003US6613689 Magnetically enhanced plasma oxide etch using hexafluorobutadiene
09/02/2003US6613688 Semiconductor device and process for generating an etch pattern
09/02/2003US6613687 Reverse reactive ion patterning of metal oxide films
09/02/2003US6613686 Method of etching silicon nitride film and method of producing semiconductor device
09/02/2003US6613685 Method for supporting a semiconductor wafer during processing
09/02/2003US6613684 Semiconductor device and method for forming contact holes in a semiconductor device
09/02/2003US6613683 Method of manufacturing a contact hole of a semiconductor device
09/02/2003US6613682 Method for in situ removal of a dielectric antireflective coating during a gate etch process
09/02/2003US6613681 Method of removing etch residues
09/02/2003US6613680 Method of manufacturing a semiconductor device
09/02/2003US6613678 Process for manufacturing a semiconductor substrate as well as a semiconductor thin film, and multilayer structure
09/02/2003US6613677 Long range ordered semiconductor interface phase and oxides
09/02/2003US6613676 Process of reclamation of SOI substrate and reproduced substrate
09/02/2003US6613675 Methods, apparatuses, and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes
09/02/2003US6613674 Semiconductor processing methods of forming integrated circuitry, and methods of forming dynamic random access memory circuitry
09/02/2003US6613673 Technique for elimination of pitting on silicon substrate during gate stack etch
09/02/2003US6613672 Apparatus and process of fabricating a trench capacitor
09/02/2003US6613671 Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
09/02/2003US6613670 Method for forming tungsten bit line and devices including the same
09/02/2003US6613669 Semiconductor device and method for manufacturing the same
09/02/2003US6613668 Two layer liner for dual damascene via
09/02/2003US6613667 Forming an interconnect of a semiconductor device
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