Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2003
09/16/2003US6620693 Non-volatile memory and fabrication thereof
09/16/2003US6620692 Method of forming a metal oxide semiconductor transistor with self-aligned channel implant
09/16/2003US6620691 Semiconductor trench device with enhanced gate oxide integrity structure
09/16/2003US6620690 Method of fabricating flash memory device using self-aligned non-exposure pattern formation process
09/16/2003US6620689 Method of fabricating a flash memory cell using angled implant
09/16/2003US6620688 Method for fabricating an extended drain metal oxide semiconductor field effect transistor with a source field plate
09/16/2003US6620687 Method of making non-volatile memory with sharp corner
09/16/2003US6620686 Methods of forming capacitors having a polymer on a portion thereof that inhibits the formation of hemispherical grain (HSG) nodules on that portion and capacitors formed thereby
09/16/2003US6620685 Method for fabricating of semiconductor memory device having a metal plug or a landing pad
09/16/2003US6620684 Method of manufacturing nonvolatile memory cell
09/16/2003US6620683 Twin-bit memory cell having shared word lines and shared bit-line contacts for electrically erasable and programmable read-only memory (EEPROM) and method of manufacturing the same
09/16/2003US6620682 Set of three level concurrent word line bias conditions for a nor type flash memory array
09/16/2003US6620681 Semiconductor device having desired gate profile and method of making the same
09/16/2003US6620680 Method of forming a contact structure and a container capacitor structure
09/16/2003US6620679 Method to integrate high performance 1T ram in a CMOS process using asymmetric structure
09/16/2003US6620678 Integrated circuit device formed with high Q MIM capacitor
09/16/2003US6620677 Support liner for isolation trench height control in vertical DRAM processing
09/16/2003US6620676 Structure and methods for process integration in vertical DRAM cell fabrication
09/16/2003US6620675 Increased capacitance trench capacitor
09/16/2003US6620674 Semiconductor device with self-aligned contact and its manufacture
09/16/2003US6620673 Thin film capacitor having multi-layer dielectric film including silicon dioxide and tantalum pentoxide
09/16/2003US6620672 SOI DRAM with buried capacitor under the digit lines utilizing a self aligning penetrating storage node contact formation
09/16/2003US6620671 Method of fabricating transistor having a single crystalline gate conductor
09/16/2003US6620670 Process conditions and precursors for atomic layer deposition (ALD) of AL2O3
09/16/2003US6620669 Manufacture of trench-gate semiconductor devices
09/16/2003US6620668 Method of fabricating MOS transistor having shallow source/drain junction regions
09/16/2003US6620666 Method of manufacturing semiconductor device of dual-gate construction, and semiconductor device manufactured thereby including forming a region of over-lapping n-type and p-type impurities with lower resistance
09/16/2003US6620665 Method for fabricating semiconductor device
09/16/2003US6620664 Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same
09/16/2003US6620663 Self-aligned copper plating/CMP process for RF lateral MOS device
09/16/2003US6620662 Double recessed transistor
09/16/2003US6620661 Single crystal TFT from continuous transition metal delivery method
09/16/2003US6620660 Active matrix type display device and method of manufacturing the same
09/16/2003US6620658 Method of manufacturing a semiconductor device
09/16/2003US6620657 Method of forming a planar polymer transistor using substrate bonding techniques
09/16/2003US6620656 Method of forming body-tied silicon on insulator semiconductor device
09/16/2003US6620654 Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure
09/16/2003US6620653 Semiconductor device and method of manufacturing the same
09/16/2003US6620652 Semiconductor device and method of making the same
09/16/2003US6620651 Adhesive wafers for die attach application
09/16/2003US6620650 Chip package and method for manufacturing the same
09/16/2003US6620649 Method for selectively providing adhesive on a semiconductor device
09/16/2003US6620646 Chip size image sensor wirebond package fabrication method
09/16/2003US6620640 Method of making field emitters
09/16/2003US6620638 Testing of multi-chip electronic modules
09/16/2003US6620637 Semiconductor analysis apparatus, semiconductor analysis method and method for manufacturing semiconductor device
09/16/2003US6620636 Semiconductor manufacturing method and semiconductor manufacturing apparatus
09/16/2003US6620634 Method of accurately measuring compositions of thin film shape memory alloys
09/16/2003US6620632 Method for evaluating impurity concentrations in semiconductor substrates
09/16/2003US6620631 Plasma etch method for forming patterned layer with enhanced critical dimension (CD) control
09/16/2003US6620630 System and method for determining and controlling contamination
09/16/2003US6620575 Construction of built-up structures on the surface of patterned masking used for polysilicon etch
09/16/2003US6620574 Method of treating photoresists using electrodeless UV lamps
09/16/2003US6620565 Electron beam lithography apparatus focused through spherical aberration introduction
09/16/2003US6620563 Lithography method for forming semiconductor devices on a wafer utilizing atomic force microscopy
09/16/2003US6620560 Plasma treatment of low-k dielectric films to improve patterning
09/16/2003US6620558 Strength, rigidity
09/16/2003US6620557 A main object of the present invention is to provide a photo-mask improved to ensure dimension with high accuracy. An actual pattern is provided on a substrate. A monitor mark for ensuring dimension of the actual pattern is also provided on
09/16/2003US6620534 Film having enhanced reflow characteristics at low thermal budget
09/16/2003US6620527 Aluminum multilayer formed on a substrate, aluminum crystal particles are substantially larger size in one layer, and more densely arranged also, the other layer has higher resist; interconnects on semiconductors
09/16/2003US6620526 Forming a trench in a first isolation layer. A sacrificial layer is formed along a surface of the etched substrate. A conductive layer is formed on the dielectric layer. A portion of the conductive layer is removed. A second isolation layer
09/16/2003US6620520 Zirconia toughened ceramic components and coatings in semiconductor processing equipment and method of manufacture thereof
09/16/2003US6620512 Anhydride polymers for use as curing agents in epoxy resin-based underfill material
09/16/2003US6620345 Conductive adhesive agent, packaging structure, and method for manufacturing the same structure
09/16/2003US6620336 Polishing pad, polishing apparatus and polishing method
09/16/2003US6620335 Plasma etch reactor and method
09/16/2003US6620334 Etching apparatus and etching method
09/16/2003US6620331 Method of etching an opening
09/16/2003US6620296 Target sidewall design to reduce particle generation during magnetron sputtering
09/16/2003US6620290 Plasma process apparatus
09/16/2003US6620289 Method and apparatus for asymmetric gas distribution in a semiconductor wafer processing system
09/16/2003US6620288 Substrate treatment apparatus
09/16/2003US6620285 Method for bonding substrates
09/16/2003US6620260 Substrate rinsing and drying method
09/16/2003US6620258 Method for washing instruments used in semiconductor industry
09/16/2003US6620257 Faster, more thorough contaminant removal; conveying while rotation cleaning
09/16/2003US6620251 Substrate processing method and substrate processing apparatus
09/16/2003US6620250 Method and apparatus for shielding a device from a semiconductor wafer process chamber
09/16/2003US6620248 Coating apparatus and mixing apparatus
09/16/2003US6620247 Thin polycrystalline silicon film forming apparatus
09/16/2003US6620245 Liquid coating apparatus with temperature controlling manifold
09/16/2003US6620238 Nitride semiconductor structure, method for producing a nitride semiconductor structure, and light emitting device
09/16/2003US6620215 Abrasive composition containing organic particles for chemical mechanical planarization
09/16/2003US6620037 Chemical mechanical polishing slurry useful for copper substrates
09/16/2003US6620035 Grooved rollers for a linear chemical mechanical planarization system
09/16/2003US6620028 Apparatus for cutting a wafer
09/16/2003US6619903 System and method for reticle protection and transport
09/16/2003US6619535 Working method for holding a work object by suction
09/16/2003US6619530 Wire bonding apparatus
09/16/2003US6619305 Apparatus for single disc ultrasonic cleaning
09/16/2003US6619304 Pressure chamber assembly including non-mechanical drive means
09/16/2003US6619301 Ultrasonic processing device and electronic parts fabrication method using the same
09/16/2003US6619144 Buffer system for a wafer handling system
09/16/2003US6618937 Method of assembling electronic applications and display devices
09/16/2003US6618922 Cooperating fixing jigs for aligning a plurality of lower members on a support member
09/16/2003US6618889 Disk-shaped workpiece washing apparatus
09/15/2003CA2377081A1 Method of producing an etch-resistant polymer structure using electron beam lithography
09/12/2003WO2003075368A2 Method and apparatus for induction heating of thin films
09/12/2003WO2003075367A1 Light-emitting device comprising led chip and method for manufacturing this device
09/12/2003WO2003075361A2 Monolithic integrated soi circuit with capacitor
1 ... 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 ... 6590