Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2003
09/09/2003US6617694 Semiconductor chip, semiconductor device, methods of fabricating thereof, circuit board and electronic device
09/09/2003US6617693 Semiconductor device and semiconductor chip for use therein
09/09/2003US6617691 Semiconductor device
09/09/2003US6617690 Interconnect structures containing stress adjustment cap layer
09/09/2003US6617689 Metal line and method of suppressing void formation therein
09/09/2003US6617688 Semiconductor device and flat electrodes
09/09/2003US6617684 Packaged die on PCB with heat sink encapsulant
09/09/2003US6617681 Interposer and method of making same
09/09/2003US6617680 Chip carrier, semiconductor package and fabricating method thereof
09/09/2003US6617675 Semiconductor device and semiconductor device assembly
09/09/2003US6617673 Memory card
09/09/2003US6617669 Multilayer semiconductor wiring structure with reduced alignment mark area
09/09/2003US6617668 Methods and devices using group III nitride compound semiconductor
09/09/2003US6617666 Semiconductor device with capacitor and process for manufacturing the device
09/09/2003US6617665 High-frequency integrated inductive winding
09/09/2003US6617664 Semiconductor device having a fuse and a fabrication process thereof
09/09/2003US6617663 Methods of manufacturing semiconductor devices
09/09/2003US6617662 Semiconductor device having a trench isolation structure
09/09/2003US6617660 Field effect transistor semiconductor and method for manufacturing the same
09/09/2003US6617658 Semiconductor memory device including magneto resistive element
09/09/2003US6617654 Source/drain regions are formed with two regions of an epitaxial silicon film formed on the surface of the substrate and a region formed by ion implantation and thermal diffusion of impurities into the substrate
09/09/2003US6617653 Misfet
09/09/2003US6617651 Semiconductor memory device
09/09/2003US6617650 Electrostatic discharge protection device
09/09/2003US6617648 Projection TV
09/09/2003US6617647 Insulated gate semiconductor device and method of manufacturing the same
09/09/2003US6617646 Reduced substrate capacitance high performance SOI process
09/09/2003US6617645 Semiconductor device and manufacturing method thereof
09/09/2003US6617644 Semiconductor device and method of manufacturing the same
09/09/2003US6617641 High voltage semiconductor device capable of increasing a switching speed
09/09/2003US6617639 Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling
09/09/2003US6617638 Tapered floating gate with nitride spacers to prevent reverse tunneling during programming in a split gate flash
09/09/2003US6617636 Adjustable spacers on walls of floating, controller barriers stacks
09/09/2003US6617635 High storage capacitance
09/09/2003US6617634 RuSixOy-containing adhesion layers and process for fabricating the same
09/09/2003US6617633 Vertical read-only memory and fabrication thereof
09/09/2003US6617632 Semiconductor device and a method of manufacturing the same
09/09/2003US6617631 Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device
09/09/2003US6617628 Ferroelectric memory device and method of fabricating the same
09/09/2003US6617627 Memory cell array having ferroelectric capacitors, method of fabricating the same, and ferroelectric memory device.
09/09/2003US6617626 Ferroelectric semiconductor memory device and a fabrication process thereof
09/09/2003US6617624 Metal gate electrode stack with a passivating metal nitride layer
09/09/2003US6617623 Multi-layered gate for a CMOS imager
09/09/2003US6617622 The pads on adjacent rows are offset from each other. Leads are provided on the semiconductor chip and bonding wires selectively connect the leads to the pads.
09/09/2003US6617619 Structure for a selective epitaxial HBT emitter
09/09/2003US6617612 Semiconductor device and a semiconductor integrated circuit
09/09/2003US6617611 Display unit and method of fabricating the same
09/09/2003US6617609 Between the semiconductor and gate dielectric
09/09/2003US6617595 Multi-lens type electrostatic lens, electron beam exposure apparatus and charged beam applied apparatus using the lens, and device manufacturing method using these apparatuses
09/09/2003US6617594 Method and device for ion implanting
09/09/2003US6617592 Charged particle beam system and chamber of charged particle beam system
09/09/2003US6617585 Optimized curvilinear variable axis lens doublet for charged particle beam projection system
09/09/2003US6617584 X-ray detecting device and fabricating method thereof
09/09/2003US6617553 Multi-zone resistive heater
09/09/2003US6617541 Laser etching method
09/09/2003US6617540 Wafer support fixture composed of silicon
09/09/2003US6617525 Molded stiffener for flexible circuit molding
09/09/2003US6617524 Packaged integrated circuit and method therefor
09/09/2003US6617521 Circuit board and display device using the same and electronic equipment
09/09/2003US6617514 Ceramics joint structure and method of producing the same
09/09/2003US6617510 Stress relief bend useful in an integrated circuit redistribution patch
09/09/2003US6617399 Thermosetting resin compositions comprising epoxy resins, adhesion promoters, curatives based on the combination of nitrogen compounds and transition metal complexes, and polysulfide tougheners
09/09/2003US6617266 Barium strontium titanate annealing process
09/09/2003US6617265 Photomask and method for manufacturing the same
09/09/2003US6617264 SOG materials for spacer anodic bonding and method of preparing the same
09/09/2003US6617263 Pattern forming method for flattening an organic film for a liquid crystal display device
09/09/2003US6617262 Sputtered insulating layer for wordline stacks
09/09/2003US6617261 Structure and method for fabricating GaN substrates from trench patterned GaN layers on sapphire substrates
09/09/2003US6617260 Method of manufacturing semiconductor device prevented from peeling of wirings from insulating film
09/09/2003US6617259 Method for fabricating semiconductor device and forming interlayer dielectric film using high-density plasma
09/09/2003US6617258 Method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and system for accomplishing same
09/09/2003US6617257 Method of plasma etching organic antireflective coating
09/09/2003US6617256 Method for controlling the temperature of a gas distribution plate in a process reactor
09/09/2003US6617255 Plasma processing method for working the surface of semiconductor devices
09/09/2003US6617253 Plasma etching method using polymer deposition and method of forming contact hole using the plasma etching method
09/09/2003US6617252 Monolithic low dielectric constant platform for passive components and method
09/09/2003US6617251 Method of shallow trench isolation formation and planarization
09/09/2003US6617250 Methods of depositing a layer comprising tungsten and methods of forming a transistor gate line
09/09/2003US6617248 Method for forming a ruthenium metal layer
09/09/2003US6617247 Method of processing a semiconductor wafer in a reaction chamber with a rotating component
09/09/2003US6617246 Semiconductor processing methods and integrated circuitry
09/09/2003US6617245 Etching mask, process for forming contact holes using same, and semiconductor device made by the process
09/09/2003US6617244 Etching method
09/09/2003US6617242 Method for fabricating interlevel contacts of aluminum/refractory metal alloys
09/09/2003US6617241 Method of thick film planarization
09/09/2003US6617240 Method of fabricating semiconductor device
09/09/2003US6617239 Subtractive metallization structure and method of making
09/09/2003US6617238 Method of manufacturing a metal wiring in a semiconductor device
09/09/2003US6617237 Lead-free bump fabrication process
09/09/2003US6617236 Fabrication method of wiring substrate for mounting semiconductor element and semiconductor device
09/09/2003US6617235 Method of manufacturing Group III-V compound semiconductor
09/09/2003US6617233 Process of fabricating an anti-fuse for avoiding a key hole exposed
09/09/2003US6617232 Method of forming wiring using a dual damascene process
09/09/2003US6617231 Method for forming a metal extrusion free via
09/09/2003US6617230 Use of selective ozone teos oxide to create variable thickness layers and spacers
09/09/2003US6617229 Method for manufacturing transistor of double spacer structure
09/09/2003US6617226 Semiconductor device and method for manufacturing the same
09/09/2003US6617225 Method of machining silicon
09/09/2003US6617224 Multiple stage deposition process for filling trenches
09/09/2003US6617223 Semiconductor-on-insulator structure fabrication having a temporary plug
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