Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2003
09/16/2003US6621262 Method for optimizing probe card analysis and scrub mark analysis data
09/16/2003US6621184 Substrate based pendulum motor
09/16/2003US6621172 Semiconductor device and method of fabricating the same, circuit board, and electronic equipment
09/16/2003US6621171 Semiconductor device having a wire laid between pads
09/16/2003US6621170 Semiconductor device, substrate for mounting semiconductor chip, processes for their production, adhesive, and double-sided adhesive film
09/16/2003US6621165 Semiconductor device fabricated by reducing carbon, sulphur, and oxygen impurities in a calcium-doped copper surface
09/16/2003US6621164 Chip size package having concave pattern in the bump pad area of redistribution patterns and method for manufacturing the same
09/16/2003US6621163 Electronic device having an electronic component with a multi-layer cover, and method
09/16/2003US6621161 Semiconductor encapsulated in a hollow package, made by housing a chip in a plurality of cavities of a plate-like substrate, bonding a plate-like cap to teh substrate, and separating the bonded members along space between cavities
09/16/2003US6621157 Method and device for encapsulating an electronic component in particular a semiconductor chip
09/16/2003US6621154 Semiconductor apparatus having stress cushioning layer
09/16/2003US6621149 Semiconductor chip production method and semiconductor wafer
09/16/2003US6621148 Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts, and gallium nitride semiconductor structures fabricated thereby
09/16/2003US6621147 In-process device with grooved coating layer on a semiconductor wafer for relieving surface tension
09/16/2003US6621146 Method and apparatus for the use of embedded resistance to linearize and improve the matching properties of transistors
09/16/2003US6621145 Semiconductor device having a metal-semiconductor junction with a reduced contact resistance
09/16/2003US6621143 Precision high-frequency capacitor on semiconductor substrate
09/16/2003US6621142 Precision high-frequency capacitor formed on semiconductor substrate
09/16/2003US6621136 Semiconductor device having regions of low substrate capacitance
09/16/2003US6621131 Semiconductor transistor having a stressed channel
09/16/2003US6621130 Semiconductor device and an electronic device
09/16/2003US6621129 MROM memory cell structure for storing multi level bit information
09/16/2003US6621128 Method of fabricating a MOS capacitor
09/16/2003US6621127 Semiconductor memory device with miniaturization improvement
09/16/2003US6621125 Buried channel device structure
09/16/2003US6621124 Semiconductor device and method of manufacturing same
09/16/2003US6621123 Semiconductor device, and semiconductor integrated device
09/16/2003US6621121 Vertical MOSFETs having trench-based gate electrodes within deeper trench-based source electrodes
09/16/2003US6621120 Semiconductor device
09/16/2003US6621119 Isolated stack-gate flash cell structure and its contactless flash memory arrays
09/16/2003US6621118 MOSFET, semiconductor device using the same and production process therefor
09/16/2003US6621117 Semiconductor device having memory cell and peripheral circuitry with dummy electrode
09/16/2003US6621116 Enhanced EPROM structures with accentuated hot electron generation regions
09/16/2003US6621115 Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate
09/16/2003US6621114 MOS transistors with high-k dielectric gate insulator for reducing remote scattering
09/16/2003US6621113 Self-aligned shallow trench isolation
09/16/2003US6621112 DRAM with vertical transistor and trench capacitor memory cells and methods of fabrication
09/16/2003US6621111 Capacitor structure of semiconductor device and method for forming the same
09/16/2003US6621110 Semiconductor intergrated circuit device and a method of manufacture thereof
09/16/2003US6621109 Charge coupled device with split channeled HCCD
09/16/2003US6621108 Semiconductor device and the process of manufacturing the semiconductor device
09/16/2003US6621107 Trench DMOS transistor with embedded trench schottky rectifier
09/16/2003US6621103 Semiconductor device and active matrix type display
09/16/2003US6621101 Thin-film transistor
09/16/2003US6621096 Device isolation process flow for ARS system
09/16/2003US6621092 Reflection type sensor
09/16/2003US6621090 Electron-beam sources exhibiting reduced spherical aberration, and microlithography apparatus comprising same
09/16/2003US6621082 Automatic focusing system for scanning electron microscope equipped with laser defect detection function
09/16/2003US6621064 CMOS photodiode having reduced dark current and improved light sensitivity and responsivity
09/16/2003US6621061 Exposure method and device manufacturing method using the same
09/16/2003US6621010 Substrate comprising laminate body with ceramic green sheets, breaking grooves arranged in main surface in grid pattern, multilayer ceramic elements constructed in blocks sectioned by grooves, fracture preventing member crossing grooves
09/16/2003US6620862 Sheet resin composition and process for manufacturing semiconductor device therewith
09/16/2003US6620745 Method for forming a blocking layer
09/16/2003US6620744 Insulating film formation method, semiconductor device, and production apparatus
09/16/2003US6620743 Stable, oxide-free silicon surface preparation
09/16/2003US6620742 In-situ use of dichloroethene and NH3 in an H2O steam based oxidation system to provide a source of chlorine
09/16/2003US6620741 Method for controlling etch bias of carbon doped oxide films
09/16/2003US6620740 Methods to form electronic devices
09/16/2003US6620739 Method of manufacturing semiconductor device
09/16/2003US6620738 Etchant and method for fabricating a semiconductor device using the same
09/16/2003US6620737 Plasma etching method
09/16/2003US6620736 Electrostatic control of deposition of, and etching by, ionized materials in semiconductor processing
09/16/2003US6620735 Method for processing substrates
09/16/2003US6620734 Methods of forming protective segments of material, and etch stops
09/16/2003US6620733 Use of hydrocarbon addition for the elimination of micromasking during etching of organic low-k dielectrics
09/16/2003US6620732 Method for controlling critical dimension in a polycrystalline silicon emitter and related structure
09/16/2003US6620731 Method for fabricating semiconductor components and interconnects with contacts on opposing sides
09/16/2003US6620730 Smart power device and method for fabricating the same
09/16/2003US6620729 Ion beam dual damascene process
09/16/2003US6620728 Top layers of metal for high performance IC's
09/16/2003US6620727 Aluminum hardmask for dielectric etch
09/16/2003US6620726 Method of forming metal lines having improved uniformity on a substrate
09/16/2003US6620725 Reduction of Cu line damage by two-step CMP
09/16/2003US6620724 Low resistivity deep trench fill for DRAM and EDRAM applications
09/16/2003US6620723 Formation of boride barrier layers using chemisorption techniques
09/16/2003US6620722 Bumping process
09/16/2003US6620721 Method of forming a self-aligning pad
09/16/2003US6620720 Interconnections to copper IC's
09/16/2003US6620719 Method of forming ohmic contacts using a self doping layer for thin-film transistors
09/16/2003US6620718 Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device
09/16/2003US6620717 Memory with disposable ARC for wordline formation
09/16/2003US6620716 Method for making semiconductor device
09/16/2003US6620715 Method for forming sub-critical dimension structures in an integrated circuit
09/16/2003US6620714 Method for reducing oxidation encroachment of stacked gate layer
09/16/2003US6620713 Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication
09/16/2003US6620711 Method of manufacturing a semiconductor device
09/16/2003US6620710 Forming a single crystal semiconductor film on a non-crystalline surface
09/16/2003US6620709 Fabrication of semiconductor materials and devices with controlled electrical conductivity
09/16/2003US6620708 Method for fabricating a semiconductor device utilizing hemispherical grain silicon and doping to increase capacitance
09/16/2003US6620706 Condensed memory matrix
09/16/2003US6620705 Nitriding pretreatment of ONO nitride for oxide deposition
09/16/2003US6620704 Method of fabricating low stress semiconductor devices with thermal oxide isolation
09/16/2003US6620703 Method of forming an integrated circuit using an isolation trench having a cavity formed by reflowing a doped glass mask layer
09/16/2003US6620702 Method of producing low thermal budget high dielectric constant structures
09/16/2003US6620701 Method of fabricating a metal-insulator-metal (MIM) capacitor
09/16/2003US6620700 Silicided undoped polysilicon for capacitor bottom plate
09/16/2003US6620699 Method for forming inside nitride spacer for deep trench device DRAM cell
09/16/2003US6620698 Method of manufacturing a flash memory
09/16/2003US6620697 Silicon carbide lateral metal-oxide semiconductor field-effect transistor having a self-aligned drift region and method for forming the same
09/16/2003US6620694 Method of making non volatile memory with a protective metal line
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