Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2003
12/16/2003US6665046 Exposure apparatus and device manufacturing method
12/16/2003US6665044 Apparatuses and methods for forming electronic assemblies
12/16/2003US6664839 Semiconductor integrated circuit having reduced crosstalk interference on clock signals
12/16/2003US6664806 Memory address and decode circuits with ultra thin body transistors
12/16/2003US6664798 Integrated circuit with test interface
12/16/2003US6664738 Plasma processing apparatus
12/16/2003US6664737 Dielectric barrier discharge apparatus and process for treating a substrate
12/16/2003US6664650 Method of forming an alignment key on a semiconductor wafer
12/16/2003US6664648 Apparatus for applying a semiconductor chip to a carrier element with a compensating layer
12/16/2003US6664647 Semiconductor device and a method of manufacturing the same
12/16/2003US6664646 Chip-on-board assemblies, carrier assemblies and carrier substrates using residual organic compounds to facilitate gate break
12/16/2003US6664645 Method of mounting a semiconductor chip, circuit board for flip-chip connection and method of manufacturing the same, electromagnetic wave readable data carrier and method of manufacturing the same, and electronic component module for an electromagnetic wave readable data carrier
12/16/2003US6664643 Semiconductor device and method for manufacturing the same
12/16/2003US6664642 Dummy regions are disposed in a shallow trench element isolation region; an insulating film is planarized by the chemical mechanical polishing
12/16/2003US6664641 Wiring structure for an integrated circuit
12/16/2003US6664640 Semiconductor device
12/16/2003US6664639 Contact and via structure and method of fabrication
12/16/2003US6664638 Semiconductor integrated circuit having reduced cross-talk noise
12/16/2003US6664637 Flip chip C4 extension structure and process
12/16/2003US6664636 Cu film deposition equipment of semiconductor device
12/16/2003US6664635 Lossless microstrip line in CMOS process
12/16/2003US6664634 Metal wiring pattern for memory devices
12/16/2003US6664633 Alkaline copper plating
12/16/2003US6664631 Apparatus for self-doping contacts to a semiconductor
12/16/2003US6664628 An unsingulated semiconductor wafer comprising a plurality of dice; an electronic component attached to at least two of said dice, said electronic component overlapping said at least two dice
12/16/2003US6664625 Mounting structure of a semiconductor device
12/16/2003US6664624 Semiconductor device and manufacturing method thereof
12/16/2003US6664616 Semiconductor device and manufacturing method thereof
12/16/2003US6664612 Semiconductor component having double passivating layers formed of two passivating layers of different dielectric materials
12/16/2003US6664611 Composition and method for cleaning residual debris from semiconductor surfaces
12/16/2003US6664610 Bipolar transistor and the method of manufacturing the same
12/16/2003US6664609 Stray capacity between the first emitter wiring and the second emitter wiring can be reduced
12/16/2003US6664608 Back-biased MOS device
12/16/2003US6664604 Metal gate stack with etch stop layer
12/16/2003US6664603 Semiconductor device, memory system and electronic apparatus
12/16/2003US6664602 Semiconductor device and method of manufacturing the same
12/16/2003US6664601 Method of orperating a dual mode FET & logic circuit having negative differential resistance mode
12/16/2003US6664600 Graded LDD implant process for sub-half-micron MOS devices
12/16/2003US6664598 Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control
12/16/2003US6664596 Stacked LDD high frequency LDMOSFET
12/16/2003US6664595 Power MOSFET having low on-resistance and high ruggedness
12/16/2003US6664593 Field effect transistor structure and method of manufacture
12/16/2003US6664592 A step of forming a source/drain region, which involves a high temperature treatment, is carried out prior to burying the gate insulator
12/16/2003US6664589 Prevent current leakage; intake, drain zones; barrier opersite channel; variations in work function; storage nodes
12/16/2003US6664588 NROM cell with self-aligned programming and erasure areas
12/16/2003US6664587 EEPROM cell array structure with specific floating gate shape
12/16/2003US6664586 Memory device and manufacturing method thereof
12/16/2003US6664585 Semiconductor memory device having multilayered storage node contact plug and method for fabricating the same
12/16/2003US6664584 Metal oxynitride capacitor barrier layer
12/16/2003US6664583 Metal oxynitride capacitor barrier layer
12/16/2003US6664582 Fin memory cell and method of fabrication
12/16/2003US6664581 Damascene capacitor having a recessed plate
12/16/2003US6664580 Buried PIP capacitor for mixed-mode process
12/16/2003US6664579 Magnetic random access memory using bipolar junction transistor
12/16/2003US6664578 Ferroelectric memory device and method of forming the same
12/16/2003US6664577 Semiconductor device includes gate insulating film having a high dielectric constant
12/16/2003US6664576 Polymer thin-film transistor with contact etch stops
12/16/2003US6664574 Heterojunction semiconductor device and method of manufacturing
12/16/2003US6664569 Liquid crystal display device array substrate and method of manufacturing the same
12/16/2003US6664565 Growing a low temperature growth ZnO layer on a sapphire substrate; thermally processing the low temperature growth ZnO layer; growing a high temperature growth single crystal ZnO layer on the low temperature growth layer
12/16/2003US6664562 Device integrated antenna for use in resonant and non-resonant modes and method
12/16/2003US6664554 Self-cleaning optic for extreme ultraviolet lithography
12/16/2003US6664551 Methods for detecting incidence orthogonality of a patterned beam in charged-particle-beam (CPB) microlithography, and CPB microlithography systems that perform same
12/16/2003US6664549 Wafer chuck, exposure system, and method of manufacturing semiconductor device
12/16/2003US6664541 Methods and apparatus for defect localization
12/16/2003US6664515 Circuit pattern of resistance heating elements and substrate-treating apparatus incorporating the pattern
12/16/2003US6664500 Laser-trimmable digital resistor
12/16/2003US6664497 Plasma chamber that may be formed from a metallic material and a transformer having a magnetic core surrounding a portion of the plasma chamber and having a primary winding for dissociation gases
12/16/2003US6664496 Plasma processing system
12/16/2003US6664480 Singulation methods and substrates for use with same
12/16/2003US6664202 Mixed frequency high temperature nitride CVD process
12/16/2003US6664201 Method of manufacturing anti-reflection layer
12/16/2003US6664200 Method of manufacturing a semiconductor component and polyimide etchant therefor
12/16/2003US6664199 Coating liquid for forming a silica group coating film having a small dielectric constant
12/16/2003US6664198 Method of forming a silicon nitride dielectric layer
12/16/2003US6664197 Process for etching thin-film layers of a workpiece used to form microelectronic circuits or components
12/16/2003US6664196 Method of cleaning electronic device and method of fabricating the same
12/16/2003US6664195 Method for forming damascene metal gate
12/16/2003US6664194 Photoexposure method for facilitating photoresist stripping
12/16/2003US6664193 Device isolation process flow for ARS system
12/16/2003US6664192 Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
12/16/2003US6664191 Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space
12/16/2003US6664190 Pre STI-CMP planarization scheme
12/16/2003US6664189 Removal of wafer edge defocus due to CMP
12/16/2003US6664188 Semiconductor wafer with a resistant film
12/16/2003US6664187 Laser thermal annealing for Cu seedlayer enhancement
12/16/2003US6664186 Method of film deposition, and fabrication of structures
12/16/2003US6664185 Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect
12/16/2003US6664184 Method for manufacturing semiconductor device having an etching treatment
12/16/2003US6664182 Method of improving the interlayer adhesion property of low-k layers in a dual damascene process
12/16/2003US6664181 Method for fabricating semiconductor device
12/16/2003US6664180 Method of forming smaller trench line width using a spacer hard mask
12/16/2003US6664179 Semiconductor device production method and semiconductor device production apparatus
12/16/2003US6664178 Method of forming buried interconnecting wire
12/16/2003US6664177 Dielectric ARC scheme to improve photo window in dual damascene process
12/16/2003US6664176 Method of making pad-rerouting for integrated circuit chips
12/16/2003US6664175 Method of forming ruthenium interconnect for an integrated circuit
12/16/2003US6664174 Semiconductor device and method for fabricating the same
12/16/2003US6664173 Hardmask gate patterning technique for all transistors using spacer gate approach for critical dimension control
12/16/2003US6664172 Method of forming a MOS transistor with improved threshold voltage stability
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