Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2003
12/09/2003US6661050 Memory cell structure with trench capacitor and method for fabrication thereof
12/09/2003US6661049 Microelectronic capacitor structure embedded within microelectronic isolation region
12/09/2003US6661048 Semiconductor memory device having self-aligned wiring conductor
12/09/2003US6661046 Image sensor and method for fabricating the same
12/09/2003US6661044 Method of manufacturing MOSEFT and structure thereof
12/09/2003US6661043 Doping nitrogen into side walls of trenches; reaction with lining oxide forms silicon oxynitride (SiON); polishing, filling; crown patterning to define capacitor areas
12/09/2003US6661042 One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
12/09/2003US6661040 Semiconductor device with insulating gate surrounded by impurity layers
12/09/2003US6661038 Semiconductor device and method of producing the same
12/09/2003US6661037 Low emitter resistance contacts to GaAs high speed HBT
12/09/2003US6661031 Resonant-cavity light-emitting diode and optical transmission module using the light-emitting diode
12/09/2003US6661027 Semiconductor device and its manufacturing method
12/09/2003US6661026 Thin film transistor substrate
12/09/2003US6661024 Forming organic semiconductor channel; dielectric patch functions as gate electrode; lamination, thinning layers
12/09/2003US6661022 Information processing structures
12/09/2003US6661021 Quantum size effect type micro electron gun and flat display unit using it and method for manufacturing the same
12/09/2003US6661018 Shroud nozzle for gas jet control in an extreme ultraviolet light source
12/09/2003US6661015 Pattern lock system
12/09/2003US6661009 Apparatus for tilting a beam system
12/09/2003US6660975 Method for producing flat wafer chucks
12/09/2003US6660973 Radiant heating apparatus and discharge current detecting circuit therefor
12/09/2003US6660956 Method of and apparatus for monitoring a ball forming process
12/09/2003US6660944 Circuit board having solder bumps
12/09/2003US6660943 One-package type thermosetting urethane comprising prepolymer obtained by reacting polyol with excessive polyisocyanate; fine powder-coated curing agent; storage stability; low temperature curing
12/09/2003US6660941 Electronic parts mounting board and production method thereof
12/09/2003US6660822 Hydrolyzing and polycondensing cyclic siloxane with or without an additional organosilicon in the presence of a catalyst and water, coating on a silicon substrate, and heat-curing
12/09/2003US6660700 Formulations including a 1,3-dicarbonyl compound chelating agent and copper corrosion inhibiting agents for stripping residues from semiconductor substrates containing copper structures
12/09/2003US6660680 Heating aerosols at low temperature; well-controlled microstructure and morphology
12/09/2003US6660666 Integrated processing system for forming an insulating layer of thin film transistor liquid crystal display
12/09/2003US6660665 Platen for electrostatic wafer clamping apparatus
12/09/2003US6660664 Structure and method for formation of a blocked silicide resistor
12/09/2003US6660663 Computer readable medium for holding a program for performing plasma-assisted CVD of low dielectric constant films formed from organosilane compounds
12/09/2003US6660662 Method of reducing plasma charge damage for plasma processes
12/09/2003US6660661 Integrated circuit with improved RC delay
12/09/2003US6660660 Methods for making a dielectric stack in an integrated circuit
12/09/2003US6660659 Plasma method and apparatus for processing a substrate
12/09/2003US6660658 Transistor structures, methods of incorporating nitrogen into silicon-oxide-containing layers; and methods of forming transistors
12/09/2003US6660657 Methods of incorporating nitrogen into silicon-oxide-containing layers
12/09/2003US6660656 Plasma processes for depositing low dielectric constant films
12/09/2003US6660655 Method and solution for preparing SEM samples for low-K materials
12/09/2003US6660654 Fabrication method and apparatus for fabricating a spatial structure in a semiconductor substrate
12/09/2003US6660653 Dual trench alternating phase shift mask fabrication
12/09/2003US6660652 Metal interconnection contact hole is formed according to three-step etching process using a photoresist film pattern exposing the intended locations of metal interconnection contacts as an etching mask; improved contact properties
12/09/2003US6660651 Adjustable wafer stage, and a method and system for performing process operations using same
12/09/2003US6660650 Selective aluminum plug formation and etchback process
12/09/2003US6660648 Process for manufacture of semipermeable silicon nitride membranes
12/09/2003US6660647 Method for processing surface of sample
12/09/2003US6660646 Method for plasma hardening photoresist in etching of semiconductor and superconductor films
12/09/2003US6660645 Process for etching an organic dielectric using a silyated photoresist mask
12/09/2003US6660644 Plasma etching methods
12/09/2003US6660643 Etching of semiconductor wafer edges
12/09/2003US6660642 Toxic residual gas removal by non-reactive ion sputtering
12/09/2003US6660641 Method for forming crack resistant planarizing layer within microelectronic fabrication
12/09/2003US6660639 Method of fabricating a copper damascene structure
12/09/2003US6660638 CMP process leaving no residual oxide layer or slurry particles
12/09/2003US6660636 Highly selective and complete interconnect metal line and via/contact hole filling by electroless plating
12/09/2003US6660635 Pre-LDD wet clean recipe to gain channel length scaling margin beyond sub-0.1 μm
12/09/2003US6660634 Method of forming reliable capped copper interconnects
12/09/2003US6660633 Method of reducing electromigration in a copper line by electroplating an interim copper-zinc alloy thin film on a copper surface and a semiconductor device thereby formed
12/09/2003US6660632 Applying amorphous film of metal complex to substrate, converting to metal or its oxides by thermal, photochemical or electron beam irradiation
12/09/2003US6660631 Devices containing platinum-iridium films and methods of preparing such films and devices
12/09/2003US6660630 Method for forming a tapered dual damascene via portion with improved performance
12/09/2003US6660629 Chemical mechanical polishing method for fabricating copper damascene structure
12/09/2003US6660628 Method of MOCVD Ti-based barrier metal thin films with tetrakis (methylethylamino) titanium with octane
12/09/2003US6660627 Method for planarization of wafers with high selectivities
12/09/2003US6660626 Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint
12/09/2003US6660625 Method of electroless plating copper on nitride barrier
12/09/2003US6660624 Method for reducing fluorine induced defects on a bonding pad surface
12/09/2003US6660623 Semiconductor device and method of manufacturing the same
12/09/2003US6660622 Process for removing an underlying layer and depositing a barrier layer in one reactor
12/09/2003US6660621 Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation
12/09/2003US6660620 Method of forming noble metal pattern
12/09/2003US6660619 Dual damascene metal interconnect structure with dielectric studs
12/09/2003US6660618 Reverse mask and oxide layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems
12/09/2003US6660617 Method for fabricating a semiconductor device
12/09/2003US6660615 Method and apparatus for growing layer on one surface of wafer
12/09/2003US6660614 Method for anodically bonding glass and semiconducting material together
12/09/2003US6660613 Method and device for forming an STI type isolation in a semiconductor device
12/09/2003US6660612 Design to prevent tungsten oxidation at contact alignment in FeRAM
12/09/2003US6660611 Method to form a corrugated structure for enhanced capacitance with plurality of boro-phospho silicate glass including germanium
12/09/2003US6660610 Devices having improved capacitance and methods of their fabrication
12/09/2003US6660609 Method of manufacturing a semiconductor device using laser irradiation
12/09/2003US6660608 Method for manufacturing CMOS device having low gate resistivity using aluminum implant
12/09/2003US6660607 Method for fabricating heterojunction bipolar transistors
12/09/2003US6660606 Semiconductor-on-insulator annealing method
12/09/2003US6660605 Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss
12/09/2003US6660604 Method of forming double junction region and method of forming transfer transistor using the same
12/09/2003US6660603 Higher voltage drain extended MOS transistors with self-aligned channel and drain extensions
12/09/2003US6660602 Stand-alone triggering structure for ESD protection of high voltage CMOS
12/09/2003US6660601 Semiconductor device and method for fabricating the same
12/09/2003US6660600 Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors
12/09/2003US6660599 Semiconductor device having trench isolation layer and method for manufacturing the same
12/09/2003US6660598 Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
12/09/2003US6660597 Method for manufacturing semiconductor integrated circuit device
12/09/2003US6660596 Double planar gated SOI MOSFET structure
12/09/2003US6660595 Implantation method for simultaneously implanting in one region and blocking the implant in another region
12/09/2003US6660594 Methods of forming integrated circuit devices having gate oxide layers with different thicknesses and integrated circuit devices formed thereby
12/09/2003US6660593 Method for fabricating oxide layers with different thicknesses
12/09/2003US6660592 Fabricating a DMOS transistor
12/09/2003US6660591 Trench-gate semiconductor devices having a channel-accommodating region and their methods of manufacture
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