Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2003
12/18/2003US20030232494 Dual damascene copper interconnect to a damascene tungsten wiring level
12/18/2003US20030232493 Semiconductor power device and method of formation
12/18/2003US20030232492 Semiconductor device package and method of making the same
12/18/2003US20030232491 Semiconductor device fabrication method
12/18/2003US20030232490 Method for manufacturing semiconductor device
12/18/2003US20030232489 Methods for manufacturing a hybrid integrated circuit device
12/18/2003US20030232488 Wafer level packaging
12/18/2003US20030232487 Fabrication of substrates with a useful layer of monocrystalline semiconductor material
12/18/2003US20030232486 Semiconductor device and method of manufacturing the same
12/18/2003US20030232484 Method of fabricating memory device
12/18/2003US20030232483 Method of manufacturing semiconductor memory
12/18/2003US20030232482 Microelectronic fabrication having fabricated therein spatially overlapping capacitor structures
12/18/2003US20030232481 Microelectronic fabrication having sidewall passivated microelectronic capacitor structure fabricated therein
12/18/2003US20030232480 Method of manufacturing semiconductor device
12/18/2003US20030232479 Method of manufacturing ferroelectric capacitor
12/18/2003US20030232478 Method of manufacturing a hetero-junction bipolar transistor
12/18/2003US20030232476 Method for fabricating a semiconductor component having at least one transistor cell and an edge cell
12/18/2003US20030232475 Method of fabricating LDMOS semiconductor devices
12/18/2003US20030232474 Pitch reduction in semiconductor fabrication
12/18/2003US20030232473 Gate electrode doping method for forming semiconductor integrated circuit microelectronic fabrication with varying effective gate dielectric layer thicknesses
12/18/2003US20030232472 Methods of fabbricating a stack-gate non-volatile memory device and its contactless memory arrays
12/18/2003US20030232471 Semiconductor device and method of fabricating the same
12/18/2003US20030232470 Integrated semiconductor memory and fabrication method
12/18/2003US20030232469 Method for planarizing deposited film
12/18/2003US20030232468 Semiconductor device and a method for fabricating the device
12/18/2003US20030232467 High mobility transistors in SOI and method for forming
12/18/2003US20030232466 Diffusion barrier layer in semiconductor substrates to reduce copper contamination from the back side
12/18/2003US20030232465 Method of introducing ion and method of manufacturing semiconductor device
12/18/2003US20030232464 Elevated source drain disposable spacer CMOS
12/18/2003US20030232461 Methods for packaging image sensitive electronic devices
12/18/2003US20030232459 Manufacturing method for electro-optical device, electro-optical device, manufacturing method for semiconductor device,semiconductor device, projection-type display apparatus, and electronic apparatus
12/18/2003US20030232457 Method for fabricating a nitride semiconductor device
12/18/2003US20030232456 Thin film transistors of a thin film transistor liquid crystal display and method for fabricating the same
12/18/2003US20030232454 Optical metrology of single features
12/18/2003US20030232453 Conductive thin film, a capacitor using the same and a method of manufacturing thereof
12/18/2003US20030232286 Forming a photosensitive layer including solvent and polysiloxane on a substrate, forming a latent image, contacting with a metal colloid solution where exposed parts adsorb metal colloid; optical filters, catalyst films
12/18/2003US20030232285 A damascene metal oxide semiconductor field effect transistor (MOSFET); depositing pad and dielectric layers; defining a gate trench to expose the substrate, forming gate dielectric, conductive layer and cap and removing dielectric
12/18/2003US20030232284 Comprising read only memory(ROM) and nitride ROM (NROM) by utilizing nitride ROM; forming field oxide layers on a surface of a substrate to define an active area of each device
12/18/2003US20030232282 Microelectronic substrate edge bead processing apparatus and method
12/18/2003US20030232279 Negative resist composition comprising base polymer having epoxy ring and Si-containing crosslinker and patterning method for semiconductor device using the same
12/18/2003US20030232276 Fluorinated molecules and methods of making and using same
12/18/2003US20030232274 Photoacid-labile polymers and photoresists comprising same
12/18/2003US20030232273 For imaging short wavelengths; acetal group deblocks in the presence of a photoacid; for example a tetrapolymer of tert-butyl acrylate, p-vinylphenol and its 1-tert-butyoxyethyl ether and 1-(trimethylnorborn-2-yl)oxyethyl ether
12/18/2003US20030232270 Chemical amplified photoresist compositions
12/18/2003US20030232258 Using a charged particle beam to eliminate attached particles from the result of splashing, correcting defects; semiconductor wafer
12/18/2003US20030232257 Apertures connecting to each other, exposing at a predetermined distance; exposing a single crystal semiconductor wafer, a glass substrate for a liquid crystal display
12/18/2003US20030232254 Photolithography process for making semiconductor devices, etching to form a deep trench in the substrate
12/18/2003US20030232252 Multi-tiered lithographic template and method of formation and use
12/18/2003US20030232251 An adjacent opaque part area with a transmission part area, by reducing the amount of exposing radiation transmitted through the area, improve the geometrical shape and dimensional accuracy of a photoresist pattern
12/18/2003US20030232174 Method of making a flexible substrate containing self-assembling microstructures
12/18/2003US20030232142 Volatile copper(II) complexes for deposition of copper films by atomic layer deposition
12/18/2003US20030232137 Introducing into the vacuum chamber gaseous reagent precursors selected from an organosilane and organosilxoane, and a porogen, heating to deposit a film containing pyrogen, removing porogen to form a porous film with low dielectric
12/18/2003US20030232131 Changing fluid photosensitive material into a photosensitive material having a band form, having length longer than width, applying such material to the first surface to stabilize photosensitive material
12/18/2003US20030231950 Semiconductor wafer position shift measurement and correction
12/18/2003US20030231694 Temperature-measuring device
12/18/2003US20030231534 Data latch circuit having anti-fuse elements
12/18/2003US20030231525 Semiconductor memory device having a reference cell
12/18/2003US20030231524 Semiconductor memory device
12/18/2003US20030231521 Semiconductor memory device and semiconductor device
12/18/2003US20030231520 Magnetic memory element having controlled nucleation site in data layer
12/18/2003US20030231469 Tray for electronic components
12/18/2003US20030231458 Metal-insulator-metal (MIM) capacitor and method for fabricating the same
12/18/2003US20030231441 Protected dual-voltage microcircuit power arrangement
12/18/2003US20030231416 Method for manufacturing optical element
12/18/2003US20030231415 Method and apparatus for managing actinic intensity transients in a lithography mirror
12/18/2003US20030231412 Apparatus for positioning an optical element in a structure
12/18/2003US20030231290 Method and apparatus for exposure
12/18/2003US20030231289 Exposure apparatus, substrate processing unit and lithographic system, and device manufacturing method
12/18/2003US20030231263 Active matrix display device and manufacturing method thereof
12/18/2003US20030231093 Microelectronic inductor structure with annular magnetic shielding layer
12/18/2003US20030231052 Semiconductor integrated circuit with constant internal power supply voltage
12/18/2003US20030231043 Integrated circuit device with clock skew reduced
12/18/2003US20030230986 Ion implantation ion source, system and method
12/18/2003US20030230854 Loadlock apparatus and structure for creating a seal between an elevator drive shaft and the loadlock chamber thereof
12/18/2003US20030230815 Semiconductor memory device
12/18/2003US20030230814 Maleimide containing monomer, cure initiator and polymers; controlled bond line thickness and uniformity; semiconductor packaging; stacking without need for spacer die
12/18/2003US20030230812 Semiconductor interconnection structure with TaN and method of forming the same
12/18/2003US20030230811 Integrated circuit devices including raised source/drain structures having different heights and methods of forming same
12/18/2003US20030230810 Semiconductor device including evaluation elements
12/18/2003US20030230809 Semiconductor device and method of manufacturing same
12/18/2003US20030230808 High aspect ratio fill method and resulting structure
12/18/2003US20030230806 Method for manufacturing semiconductor device and electronic device and method for calculating connection condition
12/18/2003US20030230803 Semiconductor device
12/18/2003US20030230800 Semiconductor device manufacturing method, semiconductor device, and semiconductor device unit
12/18/2003US20030230798 Wafer level MEMS packaging
12/18/2003US20030230796 Electrical connection for connecting a plurality of bonding pads includes first bonding pad and a bump disposed on first bonding pad, first wire stitch bonded to bump and second wire ball bonded to stitch bond of first wire
12/18/2003US20030230794 Semiconductor fabrication method and apparatus, and semiconductor device
12/18/2003US20030230793 Support for microelectronic, microoptoelectronic or micromechanical devices
12/18/2003US20030230790 Polishing of conductive layers in fabrication of integrated circuits
12/18/2003US20030230789 Base for a NPN bipolar transistor
12/18/2003US20030230788 Semiconductor device
12/18/2003US20030230786 Excellent electrical characteristics of MOS transistor devices by efficiently preventing a junction short circuit between sources and drains in a bulk area even if channel distance between sources and drains is reduced due to high integration
12/18/2003US20030230785 Semiconductor device having silicon oxide film
12/18/2003US20030230784 Semiconductor device and method for fabricating the same
12/18/2003US20030230783 Integrated memory circuit and method of forming an integrated memory circuit
12/18/2003US20030230782 Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof
12/18/2003US20030230780 Fully silicided NMOS device for electrostatic discharge protection
12/18/2003US20030230779 Semiconductor device and method for manufacturing the same
12/18/2003US20030230778 SOI structure having a SiGe Layer interposed between the silicon and the insulator
12/18/2003US20030230777 MOSFET and a method for manufacturing the same
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