| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 04/06/2004 | US6716770 Vapor deposition using organosilicon compound and fluorohydrocarbon plasma; dielectric |
| 04/06/2004 | US6716769 Use of a plasma source to form a layer during the formation of a semiconductor device |
| 04/06/2004 | US6716768 Method of manufacturing thin-film transistor, and liquid-crystal display |
| 04/06/2004 | US6716767 Contact planarization materials that generate no volatile byproducts or residue during curing |
| 04/06/2004 | US6716766 Process variation resistant self aligned contact etch |
| 04/06/2004 | US6716765 Plasma clean for a semiconductor thin film deposition chamber |
| 04/06/2004 | US6716764 Method of forming first level of metallization in DRAM chips |
| 04/06/2004 | US6716763 Method of controlling striations and CD loss in contact oxide etch |
| 04/06/2004 | US6716761 Method of forming fine patterns |
| 04/06/2004 | US6716760 Method for forming a gate of a high integration semiconductor device including forming an etching prevention or etch stop layer and anti-reflection layer |
| 04/06/2004 | US6716759 Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device |
| 04/06/2004 | US6716758 Aspect ratio controlled etch selectivity using time modulated DC bias voltage |
| 04/06/2004 | US6716757 Method for forming bottle trenches |
| 04/06/2004 | US6716756 Method for forming capacitor of semiconductor device |
| 04/06/2004 | US6716755 Composition and method for planarizing surfaces |
| 04/06/2004 | US6716754 Methods of forming patterns and molds for semiconductor constructions |
| 04/06/2004 | US6716753 Method for forming a self-passivated copper interconnect structure |
| 04/06/2004 | US6716752 Method of forming silicon oxide layer and method of manufacturing thin film transistor thereby |
| 04/06/2004 | US6716751 Dopant precursors and processes |
| 04/06/2004 | US6716749 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device |
| 04/06/2004 | US6716747 Method of manufacturing a semiconductor apparatus with a tapered aperture pattern to form a predetermined line width |
| 04/06/2004 | US6716746 Semiconductor device having self-aligned contact and method of fabricating the same |
| 04/06/2004 | US6716745 Silicide pattern structures and methods of fabricating the same |
| 04/06/2004 | US6716744 Ultra thin tungsten metal films used as adhesion promoter between barrier metals and copper |
| 04/06/2004 | US6716743 Method of manufacturing a semiconductor device |
| 04/06/2004 | US6716742 Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics |
| 04/06/2004 | US6716741 Method of patterning dielectric layer with low dielectric constant |
| 04/06/2004 | US6716740 Method for depositing silicon oxide incorporating an outgassing step |
| 04/06/2004 | US6716739 Bump manufacturing method |
| 04/06/2004 | US6716738 Method of fabricating multilayered UBM for flip chip interconnections by electroplating |
| 04/06/2004 | US6716737 Method of forming a through-substrate interconnect |
| 04/06/2004 | US6716736 Method for manufacturing an under-bump metallurgy layer |
| 04/06/2004 | US6716735 Method for forming metal lines of semiconductor device |
| 04/06/2004 | US6716734 Low temperature sidewall oxidation of W/WN/poly-gatestack |
| 04/06/2004 | US6716733 CVD-PVD deposition process |
| 04/06/2004 | US6716732 Method for fabricating a contact pad of semiconductor device |
| 04/06/2004 | US6716731 Semiconductor device and method for reducing contact resistance between an electrode and a semiconductor substrate |
| 04/06/2004 | US6716730 Pattern formation method |
| 04/06/2004 | US6716727 Methods and apparatus for plasma doping and ion implantation in an integrated processing system |
| 04/06/2004 | US6716726 Thin film semiconductor device containing polycrystalline Si—Ge alloy and method for producing thereof |
| 04/06/2004 | US6716725 Plasma processing method and semiconductor device |
| 04/06/2004 | US6716724 Method of producing 3-5 group compound semiconductor and semiconductor element |
| 04/06/2004 | US6716723 Wafer cutting using laser marking |
| 04/06/2004 | US6716722 Method of producing a bonded wafer and the bonded wafer |
| 04/06/2004 | US6716721 Method for manufacturing a silicon wafer |
| 04/06/2004 | US6716720 Method for filling depressions on a semiconductor wafer |
| 04/06/2004 | US6716719 Method of forming biasable isolation regions using epitaxially grown silicon between the isolation regions |
| 04/06/2004 | US6716718 Method of producing a semiconductor device |
| 04/06/2004 | US6716717 Method for fabricating capacitor of semiconductor device |
| 04/06/2004 | US6716716 Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth |
| 04/06/2004 | US6716715 Dram bit lines |
| 04/06/2004 | US6716714 Semiconductor diode and method for producing the same |
| 04/06/2004 | US6716713 Dopant precursors and ion implantation processes |
| 04/06/2004 | US6716712 Process for producing two differently doped adjacent regions in an integrated semiconductor |
| 04/06/2004 | US6716711 Method for fabricating a self-aligned emitter in a bipolar transistor |
| 04/06/2004 | US6716710 Using a first liner layer as a spacer in a semiconductor device |
| 04/06/2004 | US6716709 Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps |
| 04/06/2004 | US6716708 Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby |
| 04/06/2004 | US6716707 Method for making a semiconductor device having a high-k gate dielectric |
| 04/06/2004 | US6716706 Method and system for forming a long channel device |
| 04/06/2004 | US6716705 EEPROM device having a retrograde program junction region and process for fabricating the device |
| 04/06/2004 | US6716704 Methods of fabricating read only memory devices including thermally oxidized transistor sidewalls |
| 04/06/2004 | US6716703 Method of making semiconductor memory device having sources connected to source lines |
| 04/06/2004 | US6716702 Method of forming flash memory having pre-interpoly dielectric treatment layer |
| 04/06/2004 | US6716701 Method of manufacturing a semiconductor memory device |
| 04/06/2004 | US6716699 Method for manufacturing flash memory device |
| 04/06/2004 | US6716698 Virtual ground silicide bit line process for floating gate flash memory |
| 04/06/2004 | US6716697 Method of manufacturing semiconductor device having capacitor |
| 04/06/2004 | US6716696 Method of forming a bottle-shaped trench in a semiconductor substrate |
| 04/06/2004 | US6716695 Semiconductor with a nitrided silicon gate oxide and method |
| 04/06/2004 | US6716694 Semiconductor devices and methods for manufacturing semiconductor devices |
| 04/06/2004 | US6716693 Method of forming a surface coating layer within an opening within a body by atomic layer deposition |
| 04/06/2004 | US6716692 Fabrication process and structure of laminated capacitor |
| 04/06/2004 | US6716691 Self-aligned shallow trench isolation process having improved polysilicon gate thickness control |
| 04/06/2004 | US6716690 Uniformly doped source/drain junction in a double-gate MOSFET |
| 04/06/2004 | US6716689 MOS transistor having a T-shaped gate electrode and method for fabricating the same |
| 04/06/2004 | US6716688 Irradiation of manufacturing a thin film transistor by laser irradiation |
| 04/06/2004 | US6716687 FET having epitaxial silicon growth |
| 04/06/2004 | US6716686 Method for forming channels in a finfet device |
| 04/06/2004 | US6716685 Methods for forming dual gate oxides |
| 04/06/2004 | US6716684 Method of making a self-aligned triple gate silicon-on-insulator device |
| 04/06/2004 | US6716682 SOI CMOS device with reduced DIBL |
| 04/06/2004 | US6716681 Method for manufacturing thin film transistor panel |
| 04/06/2004 | US6716680 Process for manufacturing reflective TFT-LCD with rough diffuser |
| 04/06/2004 | US6716679 Methods of forming fuse box guard rings for integrated circuit devices |
| 04/06/2004 | US6716678 Method for producing an antifuse and antifuse for the selective electrical connection of adjacent conductive regions |
| 04/06/2004 | US6716677 Microwave monolithic integrated circuit package |
| 04/06/2004 | US6716675 Semiconductor device, method of manufacturing semiconductor device, lead frame, method of manufacturing lead frame, and method of manufacturing semiconductor device with lead frame |
| 04/06/2004 | US6716674 Method of forming a semiconductor package |
| 04/06/2004 | US6716672 Three dimensional interconnection method and electronic device obtained by same |
| 04/06/2004 | US6716671 Methods of making microelectronic assemblies using compressed resilient layer |
| 04/06/2004 | US6716670 Method of forming a three-dimensional stacked semiconductor package device |
| 04/06/2004 | US6716669 High-density interconnection of temperature sensitive electronic devices |
| 04/06/2004 | US6716668 Method for forming semiconductor device |
| 04/06/2004 | US6716667 Semiconductor device manufacturing method, making negative pressure for fixing a chip on a substrate |
| 04/06/2004 | US6716666 Wafer scale molding of protective caps |
| 04/06/2004 | US6716665 Method of mounting chip onto printed circuit board in shortened working time |
| 04/06/2004 | US6716664 Functional device and method of manufacturing the same |
| 04/06/2004 | US6716663 Method for removing foreign matter, method for forming film, semiconductor device and film forming apparatus |
| 04/06/2004 | US6716660 Method for fabricating a wiring line assembly for a thin film transistor array panel substrate |