H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2004
11/02/2004	US6812121 Process for forming a low resistivity titanium silicide layer on a silicon semiconductor substrate
11/02/2004	US6812120 Method of forming floating gate of memory device
11/02/2004	US6812119 Narrow fins by oxidation in double-gate finfet
11/02/2004	US6812117 Method for creating a reconfigurable nanometer-scale electronic network
11/02/2004	US6812116 Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance
11/02/2004	US6812115 Method of filling an opening in a material layer with an insulating material
11/02/2004	US6812114 Patterned SOI by formation and annihilation of buried oxide regions during processing
11/02/2004	US6812113 Process for achieving intermetallic and/or intrametallic air isolation in an integrated circuit, and integrated circuit obtained
11/02/2004	US6812112 Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers
11/02/2004	US6812111 Methods for fabricating MOS transistors with notched gate electrodes
11/02/2004	US6812110 Methods of forming capacitor constructions, and methods of forming constructions comprising dielectric materials
11/02/2004	US6812109 Integrated decoupling capacitors
11/02/2004	US6812108 BICMOS process with low temperature coefficient resistor (TCRL)
11/02/2004	US6812107 Method for improved alignment tolerance in a bipolar transistor
11/02/2004	US6812106 Reduced dopant deactivation of source/drain extensions using laser thermal annealing
11/02/2004	US6812105 Ultra-thin channel device with raised source and drain and solid source extension doping
11/02/2004	US6812104 MIS semiconductor device and method of fabricating the same
11/02/2004	US6812103 Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects
11/02/2004	US6812102 Semiconductor device manufacturing method
11/02/2004	US6812101 Semiconductor device and method for manufacture thereof
11/02/2004	US6812100 Evaporation of Y-Si-O films for medium-k dielectrics
11/02/2004	US6812099 Method for fabricating non-volatile memory having P-type floating gate
11/02/2004	US6812098 Method for manufacturing non-volatile memory device
11/02/2004	US6812097 Method for manufacturing non-volatile memory device
11/02/2004	US6812096 Method for fabrication a flash memory device having self-aligned contact
11/02/2004	US6812095 Methods of forming floating gate transistors using STI
11/02/2004	US6812094 Method for roughening a surface of a semiconductor substrate
11/02/2004	US6812093 Method for fabricating memory cell structure employing contiguous gate and capacitor dielectric layer
11/02/2004	US6812092 Method for fabricating transistors having damascene formed gate contacts and self-aligned borderless bit line contacts
11/02/2004	US6812091 Trench capacitor memory cell
11/02/2004	US6812090 Capacitor of an integrated circuit device and method of manufacturing the same
11/02/2004	US6812089 Method of manufacturing ferroelectric memory device
11/02/2004	US6812088 Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer
11/02/2004	US6812086 Method of making a semiconductor transistor
11/02/2004	US6812084 Adaptive negative differential resistance device
11/02/2004	US6812082 Semiconductor device and manufacturing method thereof
11/02/2004	US6812081 Method of manufacturing semiconductor device
11/02/2004	US6812080 Method of producing semiconductor device
11/02/2004	US6812079 Method for a junction field effect transistor with reduced gate capacitance
11/02/2004	US6812078 Method for transferring and stacking of semiconductor devices
11/02/2004	US6812077 Method for patterning narrow gate lines
11/02/2004	US6812076 Dual silicon layer for chemical mechanical polishing planarization
11/02/2004	US6812075 Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
11/02/2004	US6812074 SOI field effect transistor element having a recombination region and method of forming same
11/02/2004	US6812073 Source drain and extension dopant concentration
11/02/2004	US6812072 Method for crystallizing amorphous film and method for fabricating LCD by using the same
11/02/2004	US6812071 Method of producing crystalline semiconductor film and semiconductor device from the film
11/02/2004	US6812069 Method for improving semiconductor process wafer CMP uniformity while avoiding fracture
11/02/2004	US6812068 Semiconductor device encapsulators, methods of encapsulating semiconductor devices and methods of forming electronic packages
11/02/2004	US6812067 Method for integrating compound semiconductor with substrate or high thermal conductivity
11/02/2004	US6812066 Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
11/02/2004	US6812064 Ozone treatment of a ground semiconductor die to improve adhesive bonding to a substrate
11/02/2004	US6812062 Molded wafer scale cap
11/02/2004	US6812061 Method and apparatus for assembling an array of micro-devices
11/02/2004	US6812060 Multilayer flexible wiring boards and processes for manufacturing multilayer flexible wiring boards
11/02/2004	US6812059 Method of manufacturing a photodiode to have an active region with a convex-lens-shaped surface
11/02/2004	US6812054 TFT type optical detecting sensor implementing different TFTs and the fabricating method thereof
11/02/2004	US6812053 Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures
11/02/2004	US6812051 Method of forming an epitaxially grown nitride-based compound semiconductor crystal substrate structure and the same substrate structure
11/02/2004	US6812047 Evaluating a geometric or material property of a multilayered structure
11/02/2004	US6812046 Method and apparatus for electronically aligning capacitively coupled chip pads
11/02/2004	US6812044 Advanced control for plasma process
11/02/2004	US6812043 Method for forming a carbon doped oxide low-k insulating layer
11/02/2004	US6812042 Capacitor and method for fabricating ferroelectric memory device with the same
11/02/2004	US6812041 Method of manufacturing ferroelectric capacitor using a sintering assistance film
11/02/2004	US6812040 Method of fabricating a self-aligned via contact for a magnetic memory element
11/02/2004	US6812039 Method for producing a magnetic tunnel contact and magnetic tunnel contact
11/02/2004	US6811962 Solution of a low concentration is supplied first onto a wafer and left to stand to permit a developing reaction to proceed, followed by further supplying a developing solution of a higher concentration, letting it stand and rinsing
11/02/2004	US6811960 Provides photoresist monomers, photoresist polymers derived from the same, processes for producing such photoresist polymers, photoresist compositions comprising such polymers, and processes for producing a photoresist pattern using such
11/02/2004	US6811956 Sidewalls
11/02/2004	US6811947 Resin, which is decomposed by the action of an acid to increase solubility in an alkali developing solution
11/02/2004	US6811939 Focus monitoring method, focus monitoring system, and device fabricating method
11/02/2004	US6811935 Includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts, applying sub-resolution assist features
11/02/2004	US6811914 Electrochemical solid-state device comprising b-site rich lanthanum calcium manganite
11/02/2004	US6811892 For use with electronic/flip chip packaging; requires reflow temperatures compatible with circuit board assembly processes; improved reliability over eutectics under high temperature processing
11/02/2004	US6811817 Method for reducing pattern dimension in photoresist layer
11/02/2004	US6811816 Method and apparatus for forming deposition film, and method for treating substrate
11/02/2004	US6811738 Manufacturing method of an electronic device package
11/02/2004	US6811680 Forming a passivation layer on a substrate surface; polishing substrate in an electrolyte solution; applying an anodic bias to substrate surface; removing material from portion of substrate surface
11/02/2004	US6811675 Apparatus and method for electrolytically depositing copper on a semiconductor workpiece
11/02/2004	US6811672 Method for forming plating film and electronic component having plating film formed theron by same method
11/02/2004	US6811671 Method of controlling zinc-doping in a copper-zinc alloy thin film electroplated on a copper surface and a semiconductor device thereby formed
11/02/2004	US6811670 Method for forming cathode contact areas for an electroplating process
11/02/2004	US6811669 Methods and apparatus for improved current density and feature fill control in ECD reactors
11/02/2004	US6811661 Cathode cartridge of testing device for electroplating and testing device for electroplating
11/02/2004	US6811658 Apparatus for forming interconnects
11/02/2004	US6811634 Shrinkage inhibition, dimemsional accuracy
11/02/2004	US6811630 Ultrasonic vibration method and ultrasonic vibration apparatus
11/02/2004	US6811627 Chip mounting device and callibration method therein
11/02/2004	US6811618 Liquid processing apparatus and method
11/02/2004	US6811614 CVD reactor with substrate holder which is rotatably driven and mounted by a gas stream
11/02/2004	US6811613 Coating film forming apparatus
11/02/2004	US6811474 Polishing composition containing conducting polymer
11/02/2004	US6811473 Process for machining a wafer-like workpiece
11/02/2004	US6811471 Abrasive particles to clean semiconductor wafers during chemical mechanical planarization
11/02/2004	US6811470 Methods and compositions for chemical mechanical polishing shallow trench isolation substrates
11/02/2004	US6811468 Polishing apparatus
11/02/2004	US6811448 Pre-cleaning for silicidation in an SMOS process
11/02/2004	US6811370 Wafer handling robot having X-Y stage for wafer handling and positioning
11/02/2004	US6811369 Semiconductor fabrication apparatus, pod carry apparatus, pod carry method, and semiconductor device production method

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