Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2004
11/02/2004US6812567 Semiconductor package and package stack made thereof
11/02/2004US6812560 Press-fit chip package
11/02/2004US6812558 Wafer scale package and method of assembly
11/02/2004US6812557 Stacked type semiconductor device
11/02/2004US6812554 Semiconductor device and a method of manufacturing the same
11/02/2004US6812552 Partially patterned lead frames and methods of making and using the same in semiconductor packaging
11/02/2004US6812551 Defect-free dielectric coatings and preparation thereof using polymeric nitrogenous porogens
11/02/2004US6812549 Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument
11/02/2004US6812547 Transposed split of ion cut materials
11/02/2004US6812546 Current mirror circuit and optical signal circuit using same
11/02/2004US6812545 Epitaxial base bipolar transistor with raised extrinsic base
11/02/2004US6812542 Electric fuse whose dielectric breakdown resistance is controlled by injecting impurities into an insulating film of a capacitor structure, and a method for manufacturing the same
11/02/2004US6812541 Integrated circuit with a reduced risk of punch-through between buried layers, and fabrication process
11/02/2004US6812540 Semiconductor integrated circuit device
11/02/2004US6812538 MRAM cells having magnetic write lines with a stable magnetic state at the end regions
11/02/2004US6812537 Magnetic memory and method of operation thereof
11/02/2004US6812536 MOSFET with graded gate oxide layer
11/02/2004US6812535 Semiconductor device with a disposable gate and method of manufacturing the same
11/02/2004US6812534 Static semiconductor memory device
11/02/2004US6812533 SOI based bipolar transistor having a majority carrier accumulation layer as subcollector
11/02/2004US6812532 Semiconductor device with address programming circuit
11/02/2004US6812531 Matrix of memory cells fabricated by means of a self-aligned source process, comprising ROM memory cells, and related manufacturing process
11/02/2004US6812530 Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures
11/02/2004US6812529 Suppression of cross diffusion and gate depletion
11/02/2004US6812528 Surge protection circuit for semiconductor devices
11/02/2004US6812527 Method to control device threshold of SOI MOSFET's
11/02/2004US6812526 Trench DMOS transistor structure having a low resistance path to a drain contact located on an upper surface
11/02/2004US6812525 Trench fill process
11/02/2004US6812523 Semiconductor wafer with ultra thin doping level formed by defect engineering
11/02/2004US6812522 Lateral type power MOS transistor having trench gate formed on silicon-on-insulator (SOI) substrate
11/02/2004US6812521 Method and apparatus for improved performance of flash memory cell devices
11/02/2004US6812520 Semiconductor device and method of manufacturing the same
11/02/2004US6812519 Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same
11/02/2004US6812518 Semiconductor memory having storage cells storing multiple bits and a method of manufacturing the same
11/02/2004US6812517 Dielectric storage memory cell having high permittivity top dielectric and method therefor
11/02/2004US6812516 Field programmable logic arrays with vertical transistors
11/02/2004US6812515 Polysilicon layers structure and method of forming same
11/02/2004US6812514 High density floating gate flash memory and fabrication processes therefor
11/02/2004US6812513 Method and structure for high capacitance memory cells
11/02/2004US6812512 Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture
11/02/2004US6812511 Magnetic storage apparatus having dummy magnetoresistive effect element and manufacturing method thereof
11/02/2004US6812510 Ferroelectric capacitor, process for manufacturing thereof and ferroelectric memory
11/02/2004US6812509 Organic ferroelectric memory cells
11/02/2004US6812508 Semiconductor substrate and method for fabricating the same
11/02/2004US6812507 Non-volatile memory capable of preventing antenna effect and fabrication thereof
11/02/2004US6812506 Polysilicon linewidth measurement structure with embedded transistor
11/02/2004US6812504 TFT-based random access memory cells comprising thyristors
11/02/2004US6812499 Silicon-based film and photovoltaic element
11/02/2004US6812495 Ge photodetectors
11/02/2004US6812494 Semiconductor device
11/02/2004US6812493 Thin-film semiconductor element and method of producing same
11/02/2004US6812492 Method of fabricating a thin film transistor
11/02/2004US6812491 Semiconductor memory cell and semiconductor memory device
11/02/2004US6812490 Thin-film transistor, panel, and methods for producing them
11/02/2004US6812487 Test key and method for validating the doping concentration of buried layers within a deep trench capacitors
11/02/2004US6812486 Conductive structure and method of forming the structure
11/02/2004US6812477 Integrated circuit identification
11/02/2004US6812473 Electron beam drawing mask blank, electron beam drawing mask, and method of manufacturing the same
11/02/2004US6812472 Non-magnetic robotic manipulators for moving objects relative to a charged-particle-beam optical system
11/02/2004US6812434 Ceramic heaters, a method for producing the same and heating apparatuses used for a system for producing semiconductors
11/02/2004US6812410 Semiconductor module and method of manufacturing the same
11/02/2004US6812193 Mixture of oxidizer, corrosion resistant, abrasive particles, surfactant, halogen compound and sulfate
11/02/2004US6812167 Method for improving adhesion between dielectric material layers
11/02/2004US6812165 Manufacturing method of semiconductor integrated circuit device
11/02/2004US6812163 Semiconductor device with porous interlayer insulating film
11/02/2004US6812162 Rapid deposition of borosilicate glass films
11/02/2004US6812160 Methods of forming materials between conductive electrical components, and insulating materials
11/02/2004US6812159 Method of forming a low leakage dielectric layer providing an increased capacitive coupling
11/02/2004US6812158 Modular growth of multiple gate oxides
11/02/2004US6812156 Method to reduce residual particulate contamination in CVD and PVD semiconductor wafer manufacturing
11/02/2004US6812155 Pattern formation method
11/02/2004US6812154 Plasma etching methods
11/02/2004US6812153 Method for high aspect ratio HDP CVD gapfill
11/02/2004US6812151 Method of etching
11/02/2004US6812150 Methods for making semiconductor device structures with capacitor containers and contact apertures having increased aspect ratios
11/02/2004US6812149 Method of forming junction isolation to isolate active elements
11/02/2004US6812148 Preventing gate oxice thinning effect in a recess LOCOS process
11/02/2004US6812147 GCIB processing to improve interconnection vias and improved interconnection via
11/02/2004US6812145 Method of reducing plasma charging damage during dielectric etch process for dual damascene interconnect structures
11/02/2004US6812144 Method for forming metal wiring in a semiconductor device
11/02/2004US6812143 Process of forming copper structures
11/02/2004US6812142 Method and interlevel dielectric structure for improved metal step coverage
11/02/2004US6812141 Recessed metal lines for protective enclosure in integrated circuits
11/02/2004US6812140 Method for contact profile improvement
11/02/2004US6812138 Fill pattern generation for spin-on glass and related self-planarization deposition
11/02/2004US6812137 Method of forming coaxial integrated circuitry interconnect lines
11/02/2004US6812136 Method of making a semiconductor device having a multilayer metal film of titanium/titanium nitride/tungsten/tungsten carbide
11/02/2004US6812135 Adhesion enhancement between CVD dielectric and spin-on low-k silicate films
11/02/2004US6812134 Dual layer barrier film techniques to prevent resist poisoning
11/02/2004US6812133 Fabrication method of semiconductor device
11/02/2004US6812132 Filling small dimension vias using supercritical carbon dioxide
11/02/2004US6812131 Use of sacrificial inorganic dielectrics for dual damascene processes utilizing organic intermetal dielectrics
11/02/2004US6812130 Self-aligned dual damascene etch using a polymer
11/02/2004US6812129 Reticle for creating resist-filled vias in a dual damascene process
11/02/2004US6812128 Method of manufacturing multilayer structured semiconductor device
11/02/2004US6812127 Method of forming semiconductor device including silicon oxide with fluorine, embedded wiring layer, via holes, and wiring grooves
11/02/2004US6812126 Method for fabricating a semiconductor chip interconnect
11/02/2004US6812125 Substrate for semiconductor packaging
11/02/2004US6812123 Semiconductor devices and methods for manufacturing the same
11/02/2004US6812122 Method for forming a voltage programming element
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