Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2005
03/24/2005US20050064721 Borderless interconnection process
03/24/2005US20050064720 Process for making angled features for nanolithography and nanoimprinting
03/24/2005US20050064719 Method of controlling critical dimension microloading of photoresist trimming process by selective sidewall polymer deposition
03/24/2005US20050064718 Antireflective coating for use during the manufacture of a semiconductor device
03/24/2005US20050064717 Plasma processing apparatus
03/24/2005US20050064716 Plasma removal of high k metal oxide
03/24/2005US20050064715 Strained semiconductor structures
03/24/2005US20050064714 Method for controlling critical dimensions during an etch process
03/24/2005US20050064713 [method of fabricating flash memory]
03/24/2005US20050064712 Method of polishing a semiconductor substrate, post-cmp cleaning process, and method of cleaning residue from registration alignment markings
03/24/2005US20050064710 Trench capacitor DRAM cell using buried oxide as array top oxide
03/24/2005US20050064709 Grinding pad and method of producing the same
03/24/2005US20050064708 Via and metal line interface capable of reducing the incidence of electro-migration induced voids
03/24/2005US20050064707 Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
03/24/2005US20050064706 Methods for forming cobalt layers including introducing vaporized cobalt precursors and methods for manufacturing semiconductor devices using the same
03/24/2005US20050064705 Method for producing thin metal-containing layers having a low electrical resistance
03/24/2005US20050064704 Manufacturing method of electronic components embedded substrate
03/24/2005US20050064703 Substrate processing method
03/24/2005US20050064702 Interconnects forming method and interconnects forming apparatus
03/24/2005US20050064701 Formation of low resistance via contacts in interconnect structures
03/24/2005US20050064700 Method of plating a metal or metal or metal compound on a semiconductor substrate that includes using the same main component in both plating and etching solutions
03/24/2005US20050064699 Method of manufacturing semiconductor device
03/24/2005US20050064698 Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical properties
03/24/2005US20050064697 Ultra-fine contact alignment
03/24/2005US20050064696 Methods relating to forming interconnects and resulting assemblies
03/24/2005US20050064695 System having semiconductor component with encapsulated, bonded, interconnect contacts
03/24/2005US20050064694 Method and system for packaging ball grid arrays
03/24/2005US20050064693 Novel bonding pad structure to minimize IMD cracking
03/24/2005US20050064692 Method of forming integrated circuit contacts
03/24/2005US20050064691 Semiconductor devices and methods for fabricating a silicide of a semiconductor device
03/24/2005US20050064690 Process options of forming silicided metal gates for advanced cmos devices
03/24/2005US20050064689 Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device
03/24/2005US20050064688 Methods for fabricating semiconductor devices
03/24/2005US20050064687 Silicide proximity structures for cmos device performance improvements
03/24/2005US20050064686 Strained silicon on relaxed sige film with uniform misfit dislocation density
03/24/2005US20050064685 Method of manufacturing semiconductor device
03/24/2005US20050064684 Process for deposition of semiconductor films
03/24/2005US20050064683 Method and apparatus for supporting wafers for die singulation and subsequent handling
03/24/2005US20050064682 Failure analysis methods and systems
03/24/2005US20050064681 Support structure for thinning semiconductor substrates and thinning methods employing the support structure
03/24/2005US20050064680 Device and method for bonding wafers
03/24/2005US20050064679 Consolidatable composite materials, articles of manufacture formed therefrom, and fabrication methods
03/24/2005US20050064678 Method of fabricating a semiconductor component with active regions separated by isolation trenches
03/24/2005US20050064677 Mixed signal integrated circuit with improved isolation
03/24/2005US20050064676 Method of forming alignment mark
03/24/2005US20050064675 Method of fabricating crystalline silicon and switching device using crystalline silicon
03/24/2005US20050064674 Etching method for manufacturing semiconductor device
03/24/2005US20050064673 High capacitive density stacked decoupling capacitor structure
03/24/2005US20050064672 Bipolar transistor with lattice matched base layer
03/24/2005US20050064671 Reduction of channel hot carrier effects in transistor devices
03/24/2005US20050064670 Depletion drain-extended MOS transistors and methods for making the same
03/24/2005US20050064669 Method for forming a semiconductor device having isolation regions
03/24/2005US20050064668 Methods of code programming a mask ROM device
03/24/2005US20050064667 Semiconductor device manufacturing method
03/24/2005US20050064666 Flash memory and methods of fabricating flash memory
03/24/2005US20050064664 Manufacturing method of semiconductor integrated circuit device
03/24/2005US20050064663 Method of manufacturing semiconductor device
03/24/2005US20050064662 [method of fabricating flash memory]
03/24/2005US20050064661 Method of fabricating a flash memory cell
03/24/2005US20050064660 Methods of fabricating integrated circuit devices that utilize doped poly-Si1-xGex conductive plugs as interconnects
03/24/2005US20050064659 Capacitorless 1-transistor DRAM cell and fabrication method
03/24/2005US20050064658 Two-mask process for metal-insulator-metal capacitors and single mask process for thin film resistors
03/24/2005US20050064657 Interdigital capacitor and method for adjusting the same
03/24/2005US20050064656 Selective polysilicon stud growth
03/24/2005US20050064655 Nonvolatile memory cells having split gate structure and methods of fabricating the same
03/24/2005US20050064654 Process for manufacturing a dual charge storage location memory cell
03/24/2005US20050064653 Semiconductor devices having metal containing N-type and P-type gate electrodes and methods of forming the same
03/24/2005US20050064651 Methods for forming a device isolation structure in a semiconductor device
03/24/2005US20050064650 Fabrication method for microstructures with high aspect ratios
03/24/2005US20050064649 Semiconductor device and method for manufacturing the same
03/24/2005US20050064648 Method for forming wiring pattern, method for manufacturing semiconductor device, electro-optic device and electronic equipment
03/24/2005US20050064647 Wire, method of manufacturing the wire, and electromagnet using the wire
03/24/2005US20050064646 NFETs using gate induced stress modulation
03/24/2005US20050064645 Method of making adaptive negative differential resistance device
03/24/2005US20050064644 Process for producing microelectromechanical components and a housed microelectromechanical component
03/24/2005US20050064643 Method for isolation layer for a vertical DRAM
03/24/2005US20050064642 Optical component and method of manufacturing the same
03/24/2005US20050064641 Solution applying apparatus and method
03/24/2005US20050064640 Semiconductor device and method for manufacturing the same
03/24/2005US20050064639 Method of fabricating SiC semiconductor device
03/24/2005US20050064638 Method for the selective formation of a silicide on a wafer
03/24/2005US20050064637 [method of manufacturing nmos transistor with p-type gate]
03/24/2005US20050064636 Method and apparatus for fabricating CMOS field effect transistors
03/24/2005US20050064635 METHOD FOR AVOIDING OXIDE UNDERCUT DURING PRE-SILICIDE CLEAN FOR THIN SPACER FETs
03/24/2005US20050064634 Structure and method for placement, sizing and shaping of dummy structures
03/24/2005US20050064633 Film pattern formation method, device and method for manufacturing the same, electro-optical device, electronic device, and method for manufacturing active matrix substrate
03/24/2005US20050064632 Soi wafer and method for manufacturing soi wafer
03/24/2005US20050064631 Multi-chip semiconductor package and fabrication method thereof
03/24/2005US20050064630 Method for producing a protection for chip edges and system for the protection of chip edges
03/24/2005US20050064629 Tungsten-copper interconnect and method for fabricating the same
03/24/2005US20050064628 Electrical or electronic component and method of producing same
03/24/2005US20050064627 Method for manufacturing an electronic circuit device and electronic circuit device
03/24/2005US20050064625 Method for mounting passive components on wafer
03/24/2005US20050064624 Method of manufacturing wafer level chip size package
03/24/2005US20050064623 Semiconductor layers with roughness patterning
03/24/2005US20050064622 Mask, method of manufacturing a mask, method of manufacturing an organic electroluminescence device, and organic electroluminiescence device
03/24/2005US20050064621 Method for manufacturing CMOS image sensor
03/24/2005US20050064620 CMOS image sensor and method for manufacturing the same
03/24/2005US20050064616 Semiconductor channel on insulator structure
03/24/2005US20050064615 Method for separating sapphire wafer into chips using dry-etching
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