Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2005
03/31/2005WO2004082010A3 Method of improving interlayer adhesion
03/31/2005WO2004081990A3 Coated metal stud bump formed by a coated wire for flip chip
03/31/2005WO2004077505A3 Critical dimension variation compensation across a wafer by means of local wafer temperature control
03/31/2005WO2004077503A3 Controlled fabrication of gaps in electrically conducting structures
03/31/2005WO2004057660A3 Method for producing a sublithographic gate structure for field effect transistors, and for producing an associated field effect transistor, an associated inverter, and an associated inverter structure
03/31/2005US20050071797 Automatic layout system, layout model generation system, layout model verification system, and layout model
03/31/2005US20050071101 Apparatus and method for inspecting semiconductor device
03/31/2005US20050071043 Method for providing distributed material management and flow control in an integrated circuit factory
03/31/2005US20050071039 System and method for using first-principles simulation to provide virtual sensors that facilitate a semiconductor manufacturing process
03/31/2005US20050071036 System and method for using first-principles simulation to characterize a semiconductor manufacturing process
03/31/2005US20050070217 Polishing pad and fabricating method thereof
03/31/2005US20050070216 Resilient polishing pad for chemical mechanical polishing
03/31/2005US20050070215 Chemical mechanical polishing apparatus having conditioning cleaning device
03/31/2005US20050070211 Barrier polishing fluid
03/31/2005US20050070174 Electrical joint forming member and plasma processing apparatus
03/31/2005US20050070128 Post-deposition treatment to enhance properties of Si-O-C low K films
03/31/2005US20050070127 Method for adjusting capacitance of an on-chip capacitor
03/31/2005US20050070126 System and method for forming multi-component dielectric films
03/31/2005US20050070125 Photo resist dispensing system and method
03/31/2005US20050070124 Direct photo-patterning of nanoporous organosilicates, and method of use
03/31/2005US20050070123 Method for forming a thin film and method for fabricating a semiconductor device
03/31/2005US20050070122 Thin germanium oxynitride gate dielectric for germanium-based devices
03/31/2005US20050070121 Variable temperature and dose atomic layer deposition
03/31/2005US20050070120 Methods and devices for an insulated dielectric interface between high-k material and silicon
03/31/2005US20050070119 Method to make a weight compensating/tuning layer on a substrate
03/31/2005US20050070118 Fabrication process for preparing recording head sliders made from silicon substrates with SiO2 overcoats
03/31/2005US20050070117 Etch with ramping
03/31/2005US20050070116 Process for low k dielectric plasma etching with high selectivity to deep uv photoresist
03/31/2005US20050070115 Method of making relaxed silicon-germanium on insulator via layer transfer with stress reduction
03/31/2005US20050070114 Selective etching processes for In2O3 thin films in FeRAM device applications
03/31/2005US20050070113 Low resistance T-shaped ridge structure
03/31/2005US20050070112 Method for controlling trench depth in shallow trench isolation features
03/31/2005US20050070111 Etching method and computer storage medium storing program for controlling same
03/31/2005US20050070110 Etching solution, etching method and method for manufacturing semiconductor device
03/31/2005US20050070109 Novel slurry for chemical mechanical polishing of metals
03/31/2005US20050070108 Top oxide nitride liner integration scheme for vertical dram
03/31/2005US20050070107 Method of manufacturing photovoltaic device
03/31/2005US20050070105 Small volume process chamber with hot inner surfaces
03/31/2005US20050070104 Method and processing system for monitoring status of system components
03/31/2005US20050070103 Method and apparatus for endpoint detection during an etch process
03/31/2005US20050070102 Precision polysilicon resistor process
03/31/2005US20050070101 Silicon dioxide removing method
03/31/2005US20050070100 Low-pressure deposition of metal layers from metal-carbonyl precursors
03/31/2005US20050070099 Semiconductor integrated circuit device and method for manufacturing the same
03/31/2005US20050070098 Pre-anneal of cosi, to prevent formation of amorphous layer between ti-o-n and cosi
03/31/2005US20050070097 Atomic laminates for diffusion barrier applications
03/31/2005US20050070096 Unidirectionally conductive materials for interconnection
03/31/2005US20050070095 Protective layer during scribing
03/31/2005US20050070094 Semiconductor device having multilayer interconnection structure and manufacturing method thereof
03/31/2005US20050070093 Sacrificial dielectric planarization layer
03/31/2005US20050070092 Method for creating electrical pathways for semiconductor device structures using laser machining processes
03/31/2005US20050070091 Method of chemical mechanical polishing
03/31/2005US20050070090 Method of forming metal pattern using selective electroplating process
03/31/2005US20050070089 Method for manufacturing a semiconductor device
03/31/2005US20050070088 Circuit structures and methods of forming circuit structures with minimal dielectric constant layers
03/31/2005US20050070087 Wafer-level thick film standing-wave clocking
03/31/2005US20050070086 Semiconductor device and method for fabricating the same
03/31/2005US20050070085 Reliable metal bumps on top of I/O pads after removal of test probe marks
03/31/2005US20050070084 Substrate for pre-soldering material and fabrication method thereof
03/31/2005US20050070083 Wafer-level moat structures
03/31/2005US20050070082 Semiconductor device having a nickel/cobalt silicide region formed in a silicon region
03/31/2005US20050070081 Method for manufacturing semiconductor device
03/31/2005US20050070080 Method of forming self-aligned contact pads of non-straight type semiconductor memory device
03/31/2005US20050070079 Method to control the interfacial layer for deposition of high dielectric constant films
03/31/2005US20050070078 Indirect bonding with disappearance of bonding layer
03/31/2005US20050070077 Self-aligned SOI with different crystal orientation using WAFER bonding and SIMOX processes
03/31/2005US20050070076 Method of depositing high-quality sige on sige substrates
03/31/2005US20050070075 Laser beam processing method and laser beam machine
03/31/2005US20050070074 Method for dicing semiconductor wafer
03/31/2005US20050070072 Method for processing wafer
03/31/2005US20050070071 Method and device for controlled cleaving process
03/31/2005US20050070070 Method of forming strained silicon on insulator
03/31/2005US20050070068 Alignment mark forming method, substrate in which devices are formed, and liquid discharging head using substrate
03/31/2005US20050070067 Methods of fabricating semiconductor devices
03/31/2005US20050070066 Method for fabricating a trench capacitor having an insulation collar, which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory cell
03/31/2005US20050070065 Deep trench structure manufacturing process
03/31/2005US20050070064 Self-limited metal recess for deep trench metal fill
03/31/2005US20050070063 High performance MIS capacitor with HfO2 dielectric
03/31/2005US20050070062 MOS transistor gates with doped silicide and methods for making the same
03/31/2005US20050070061 Sacrificial dielectric planarization layer
03/31/2005US20050070060 TFT mask ROM and method for making same
03/31/2005US20050070059 Method of making thin silicon sheets for solar cells
03/31/2005US20050070058 Ild stack with improved cmp results
03/31/2005US20050070057 Semiconductor layer formation
03/31/2005US20050070056 SOI template layer
03/31/2005US20050070055 Thin film transistor and method for production thereof
03/31/2005US20050070054 Thin-film transistor device, method of manufacturing the same, thin-film transistor substrate provided therewith and display device
03/31/2005US20050070053 Template layer formation
03/31/2005US20050070051 Method of manufacturing a semiconductor device using a rigid substrate
03/31/2005US20050070050 Method of mounting wafer on printed wiring substrate
03/31/2005US20050070049 Method for fabricating wafer-level chip scale packages
03/31/2005US20050070048 Devices and methods employing high thermal conductivity heat dissipation substrates
03/31/2005US20050070047 Method of manufacturing a semiconductor device
03/31/2005US20050070046 Method of manufacturing electronic device and method of manufacturing electro-optical device
03/31/2005US20050070045 FBAR based duplexer device and manufacturing method thereof
03/31/2005US20050070044 Modified chip attach process and apparatus
03/31/2005US20050070043 Semiconductor device and method for manufacturing the same
03/31/2005US20050070042 Apparatus and method for making a tensile diaphragm with an insert
03/31/2005US20050070041 Atomic layer deposition (ALD) method with enhanced deposition rate
03/31/2005US20050070038 Display device and method of fabricating the same
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