Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2005
03/17/2005WO2005024931A1 Semiconductor device and its manufacturing method
03/17/2005WO2005024930A2 Method for producing a semiconductor component with a praseodymium oxide dielectric
03/17/2005WO2005024929A1 A selective etch process for making a semiconductor device having a high-k gate dielectric
03/17/2005WO2005024927A1 Improved method of etching silicon
03/17/2005WO2005024926A1 Substrate treating device and method of manufacturing semiconductor device
03/17/2005WO2005024925A1 Method for producing soi wafer
03/17/2005WO2005024924A1 Process for producing semiconductor device
03/17/2005WO2005024923A1 Method and device
03/17/2005WO2005024922A1 A method of forming a teos cap layer at low temperature and reduced deposition rate
03/17/2005WO2005024921A1 Exposure apparatus and device producing method
03/17/2005WO2005024920A1 Improved method of forming openings in an organic resin material
03/17/2005WO2005024919A1 A device and method for inhibiting hydrogen damage in ferroelectric capacitor devices
03/17/2005WO2005024918A1 Soi wafer and its manufacturing method
03/17/2005WO2005024917A1 Method for producing bonded wafer
03/17/2005WO2005024916A1 Method for producing soi wafer
03/17/2005WO2005024915A1 Maintenance management device, maintenance management method, maintenance management program, and information recording medium
03/17/2005WO2005024914A1 Semiconductor arrangement with thin-film resistor
03/17/2005WO2005024913A1 Integrated circuit with a capacitor and method for the production thereof
03/17/2005WO2005024912A2 Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow
03/17/2005WO2005024908A2 Laser transfer articles and method of making
03/17/2005WO2005024906A2 Structure and method for metal replacement gate of high performance device
03/17/2005WO2005024904A2 Reduction of feature critical dimensions
03/17/2005WO2005024903A2 Method and structure for improving the gate resistance of a closed cell trench power mosfet
03/17/2005WO2005024902A2 Method of forming a bond pad
03/17/2005WO2005024900A2 Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same
03/17/2005WO2005024899A2 Method to produce transistor having reduced gate height
03/17/2005WO2005024897A2 Systems and methods having a metal-semiconductor-metal (msm) photodetector with buried oxide layer
03/17/2005WO2005024856A2 Method and system for providing a magnetic element including passivation structures
03/17/2005WO2005024841A1 Programming of a memory with discrete charge storage elements
03/17/2005WO2005024672A1 Esd test array and corresponding method
03/17/2005WO2005024519A1 Optical proximity effect correction processing method allowing for dummy pattern
03/17/2005WO2005024094A2 In-situ-etch-assisted hdp deposition using sif4 and hydrogen
03/17/2005WO2005023702A1 Metal nanoparticle and method for producing same, liquid dispersion of metal nanoparticle and method for producing same, metal thin line, metal film and method for producing same
03/17/2005WO2005010240A3 Low temperature methods for hermetically sealing reservoir devices
03/17/2005WO2005008767A3 Metal bump with an insulation for the side walls and method of fabricating a chip with such a metal bump
03/17/2005WO2005001915A3 Method of producing a stacked structure by means of thin layer transfer
03/17/2005WO2005001888A3 Device and method for cleaning objects used to produce semiconductors, especially transport and cleaning containers for wafers
03/17/2005WO2004112104A3 Low temperature process for tft fabrication
03/17/2005WO2004112042A3 Non-volatile memory device
03/17/2005WO2004109781B1 Substrate for stressed systems and method for crystal growth on such a substrate
03/17/2005WO2004107452B1 Semiconductor device and method for manufacturing same
03/17/2005WO2004105435A3 Retention mechanism for heating coil of high temperature diffusion furnace
03/17/2005WO2004102671A8 Power device with high switching speed and manufacturing method thereof
03/17/2005WO2004095515B1 Methods for contracting conducting layers overlying magnetoelectronic elements of mram devices
03/17/2005WO2004093147B1 Wafer carrier cleaning system
03/17/2005WO2004079814B1 Modulated/composited cvd low-k films with improved mechanical and electrical properties for nanoelectronic devices
03/17/2005WO2004079742A3 Method of forming a flux concentrating layer of a magnetic device
03/17/2005WO2004077019A3 Capillary rise technique for the assessment of the wettability of particulate surfaces
03/17/2005WO2004059695A3 Ultrasonic levitation in a rapid thermal processing plant for wafers
03/17/2005WO2004055855B1 Gas distribution apparatus and method for uniform etching
03/17/2005WO2004053946A3 System and method for suppression of wafer temperature drift in cold-wall cvd system
03/17/2005WO2004053936A3 Multi-layer gate stack
03/17/2005WO2004025710A3 Method of heating a substrate in a variable temperature process using a fixed temperature chuck
03/17/2005WO2004016055A8 An electronic product, a body and a method of manufacturing
03/17/2005WO2003096351A3 Memories and memory circuits
03/17/2005WO2003087206A8 Patterned polymeric structures, particularly microstructures, and methods for making same
03/17/2005WO2003019626A3 Method of forming a pattern on a semiconductor wafer using an attenuated phase shifting reflective mask
03/17/2005WO2001078114A9 WAFER ORIENTATION SENSOR FOR GaAs WAFERS
03/17/2005US20050060678 Automatic placement and routing apparatus and automatic placement and routing method
03/17/2005US20050060676 Semiconductor integrated circuit and method for designing same
03/17/2005US20050060672 Automated layout transformation system and method
03/17/2005US20050060115 Low profile carrier for non-wafer form device testing
03/17/2005US20050060104 Wafer edge inspection data gathering
03/17/2005US20050060103 Method and system of diagnosing a processing system using adaptive multivariate analysis
03/17/2005US20050060098 Methods for calculating the voltage induced in a device
03/17/2005US20050059325 Wafer processing method
03/17/2005US20050059310 Method for the production of led bodies
03/17/2005US20050059266 Apparatus and method for removing fine particles during fabrication of a portable camera module
03/17/2005US20050059265 Systems and methods for processing thin films
03/17/2005US20050059264 CVD plasma assisted low dielectric constant films
03/17/2005US20050059263 Method of manufacturing semiconductor element
03/17/2005US20050059262 Transparent amorphous carbon structure in semiconductor devices
03/17/2005US20050059261 Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces
03/17/2005US20050059260 CMOS transistors and methods of forming same
03/17/2005US20050059259 Interfacial oxidation process for high-k gate dielectric process integration
03/17/2005US20050059258 Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same
03/17/2005US20050059257 Highly crystalline aluminum nitride multi-layered substrate and production process thereof
03/17/2005US20050059256 Method of forming a resist pattern and fabricating tapered features
03/17/2005US20050059255 Wafer processing techniques with enhanced alignment
03/17/2005US20050059254 Methods and apparatus of etch process control in fabrications of microstructures
03/17/2005US20050059253 Etching method in fabrications of microstructures
03/17/2005US20050059252 Self-aligned planar double-gate process by self-aligned oxidation
03/17/2005US20050059251 Constant and reducible hole bottom CD in variable post-CMP thickness and after-development-inspection CD
03/17/2005US20050059250 Fast etching system and process for organic materials
03/17/2005US20050059249 Method to shrink cell size in a split gate flash
03/17/2005US20050059248 Two-step GC etch for GC profile and process window improvement
03/17/2005US20050059247 Method for manufacturing SiC substrate
03/17/2005US20050059245 Integration of ultra low K dielectric in a semiconductor fabrication process
03/17/2005US20050059243 Film forming material, film forming method, and silicide film
03/17/2005US20050059242 Reduction of silicide formation temperature on SiGe containing substrates
03/17/2005US20050059241 Method and system for controlling the presence of fluorine in refractory metal layers
03/17/2005US20050059240 Method for forming a wiring of a semiconductor device, method for forming a metal layer of a semiconductor device and apparatus for performing the same
03/17/2005US20050059239 Foreign material removing method for capacitance type dynamic quantity sensor
03/17/2005US20050059238 Cooling system for a semiconductor device and method of fabricating same
03/17/2005US20050059237 Method for manufacturing semiconductor device
03/17/2005US20050059236 Semiconductor device and a method of manufacturing the same
03/17/2005US20050059235 Method for improving oxide layer flatness
03/17/2005US20050059234 Method of fabricating a dual damascene interconnect structure
03/17/2005US20050059233 Process for forming metal damascene structure to prevent dielectric layer peeling
03/17/2005US20050059232 Method for the post-etch cleaning of multi-level damascene structures having underlying copper metallization
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