Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2005
03/29/2005US6873532 Content addressable memory cell having improved layout
03/29/2005US6873517 Ferroelectric capacitor
03/29/2005US6873506 System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing
03/29/2005US6873476 Microlithographic reduction projection catadioptric objective
03/29/2005US6873450 Micromirrors with mechanisms for enhancing coupling of the micromirrors with electrostatic fields
03/29/2005US6873404 Stage apparatus and method of driving the same
03/29/2005US6873400 Scanning exposure method and system
03/29/2005US6873397 Exposure apparatus, gas replacing method, and method of manufacturing a semiconductor device
03/29/2005US6873396 Photolithography processing system
03/29/2005US6873379 Fabricating method of an array substrate having polysilicon thin film transistor
03/29/2005US6873273 Photonic serial digital-to-analog converter employing a heterojunction thyristor device
03/29/2005US6873166 Localized heating for defect isolation during die operation
03/29/2005US6873092 Display unit
03/29/2005US6873087 High precision orientation alignment and gap control stages for imprint lithography processes
03/29/2005US6873060 Electronic component with a semiconductor chip, method of producing an electronic component and a panel with a plurality of electronic components
03/29/2005US6873059 Semiconductor package with metal foil attachment film
03/29/2005US6873058 Multilayer; substrate, semiconductor, dielectric
03/29/2005US6873057 Damascene interconnect with bi-layer capping film
03/29/2005US6873056 Electrode-to-electrode bond structure
03/29/2005US6873055 Integrated circuit arrangement with field-shaping electrical conductor
03/29/2005US6873054 Semiconductor device and a method of manufacturing the same, a circuit board and an electronic apparatus
03/29/2005US6873053 Semiconductor device with smoothed pad portion
03/29/2005US6873052 Porous, film, wiring structure, and method of forming the same
03/29/2005US6873051 Nickel silicide with reduced interface roughness
03/29/2005US6873050 Intermediate construction having an edge defined feature
03/29/2005US6873048 System and method for integrating multiple metal gates for CMOS applications
03/29/2005US6873047 Semiconductor device and manufacturing method thereof
03/29/2005US6873046 Chip-scale package and carrier for use therewith
03/29/2005US6873044 Microwave monolithic integrated circuit package
03/29/2005US6873043 Electronic assembly having electrically-isolated heat-conductive structure
03/29/2005US6873039 Methods of making microelectronic packages including electrically and/or thermally conductive element
03/29/2005US6873038 Capacitor and semiconductor device and method for fabricating the semiconductor device
03/29/2005US6873034 Solid-state imaging device, method for producing same, and mask
03/29/2005US6873030 Metal gate electrode using silicidation and method of formation thereof
03/29/2005US6873029 Self-aligned bipolar transistor
03/29/2005US6873026 Inhomogeneous materials having physical properties decoupled from desired functions
03/29/2005US6873022 Semiconductor device and method for manufacturing the same
03/29/2005US6873021 MOS transistors having higher drain current without reduced breakdown voltage
03/29/2005US6873020 High/low work function metal alloys for integrated circuit electrodes
03/29/2005US6873019 Semiconductor device including memory cells and manufacturing method thereof
03/29/2005US6873018 Memory cell constructions comprising integrated bipolar and FET devices
03/29/2005US6873017 ESD protection for semiconductor products
03/29/2005US6873016 Semiconductor device and method of forming the same
03/29/2005US6873015 Semiconductor constructions comprising three-dimensional thin film transistor devices and resistors
03/29/2005US6873014 Semiconductor device and method of manufacturing the same
03/29/2005US6873013 Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering
03/29/2005US6873010 High performance logic and high density embedded dram with borderless contact and antispacer
03/29/2005US6873009 Vertical semiconductor device with tunnel insulator in current path controlled by gate electrode
03/29/2005US6873008 Asymmetrical devices for short gate length performance with disposable sidewall
03/29/2005US6873007 Nonvolatile semiconductor memory device and process for producing the same
03/29/2005US6873006 Semiconductor memory array of floating gate memory cells with burried floating gate and pointed channel region
03/29/2005US6873005 Programmable memory devices supported by semiconductor substrates
03/29/2005US6873004 Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof
03/29/2005US6873003 Nonvolatile memory cell
03/29/2005US6873002 Semiconductor memory device having cylinder-type stacked capacitor and method for fabricating such a semiconductor memory device
03/29/2005US6873001 Reduced size plate layer improves misalignments for CUB DRAM
03/29/2005US6873000 Storage cell field and method of producing the same
03/29/2005US6872999 Semiconductor storage device with signal wiring lines RMED above memory cells
03/29/2005US6872998 Ferroelectric memory device
03/29/2005US6872997 Method for manufacture of magneto-resistive bit structure
03/29/2005US6872996 Method of fabricating a ferroelectric stacked memory cell
03/29/2005US6872995 Ferroelectric capacitor, method of manufacturing same, and semiconductor memory device
03/29/2005US6872994 Semiconductor device having an active region whose width varies
03/29/2005US6872990 Layout method of semiconductor device
03/29/2005US6872989 Semiconductor device and method for fabricating the same
03/29/2005US6872988 Semiconductor films on flexible iridium substrates
03/29/2005US6872987 Silicon controlled rectifier ESD structures with trench isolation
03/29/2005US6872986 Nitride semiconductor device
03/29/2005US6872984 Method of sealing a hermetic lid to a semiconductor die at an angle
03/29/2005US6872982 Semiconductor device and method of fabricating the same and method of forming nitride based semiconductor layer
03/29/2005US6872980 Organic thin film transistor array substrate
03/29/2005US6872979 Semiconductor substrate with stacked oxide and SOI layers with a molten or epitaxial layer formed on an edge of the stacked layers
03/29/2005US6872978 CMOS-type thin film semiconductor device and method of fabricating the same
03/29/2005US6872977 Thin film semiconductor device, production process and information displays
03/29/2005US6872976 Thin film transistor array panel
03/29/2005US6872972 Method for forming silicon film with changing grain size by thermal process
03/29/2005US6872971 Scaffold-organized clusters and electronic made using such clusters
03/29/2005US6872970 Photoresponsive devices
03/29/2005US6872967 Nitride-based semiconductor device and manufacturing method thereof
03/29/2005US6872958 Platform positioning system
03/29/2005US6872952 Electron optical system array, method of manufacturing the same, charged-particle beam exposure apparatus, and device manufacturing method
03/29/2005US6872951 Electron optical system array, charged-particle beam exposure apparatus using the same, and device manufacturing method
03/29/2005US6872950 Electron optical system array, method of fabricating the same, charged-particle beam exposure apparatus, and device manufacturing method
03/29/2005US6872943 Method for determining depression/protrusion of sample and charged particle beam apparatus therefor
03/29/2005US6872910 Laser irradiation apparatus and method of fabricating a semiconductor device
03/29/2005US6872908 Susceptor with built-in electrode and manufacturing method therefor
03/29/2005US6872671 Insulators for high density circuits
03/29/2005US6872670 Silylation treatment unit and method
03/29/2005US6872669 PZT (111) texture through Ir texture improvement
03/29/2005US6872668 Multi-step tungsten etchback process to preserve barrier integrity in an integrated circuit structure
03/29/2005US6872667 Method of fabricating semiconductor device with separate periphery and cell region etching steps
03/29/2005US6872666 Method for making a dual damascene interconnect using a dual hard mask
03/29/2005US6872665 Process flow for dual damescene interconnect structures
03/29/2005US6872664 Dual gate nitride process
03/29/2005US6872663 Method for reworking a multi-layer photoresist following an underlayer development
03/29/2005US6872662 Method for detecting the endpoint of a chemical mechanical polishing (CMP) process
03/29/2005US6872661 Leadless plastic chip carrier with etch back pad singulation and die attach pad array
03/29/2005US6872660 Methods of forming conductive contacts
03/29/2005US6872659 Activation of oxides for electroless plating
03/29/2005US6872658 Method of fabricating semiconductor device by exposing resist mask