Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2005
03/22/2005US6870267 Off-center solder ball attach assembly
03/22/2005US6870265 Semiconductor device and manufacturing method thereof
03/22/2005US6870263 Device interconnection
03/22/2005US6870262 Wafer-bonding using solder and method of making the same
03/22/2005US6870258 Fixture suitable for use in coupling a lid to a substrate and method
03/22/2005US6870256 Semiconductor device having a thin-film circuit element provided above an integrated circuit
03/22/2005US6870254 Flip clip attach and copper clip attach on MOSFET device
03/22/2005US6870248 Semiconductor chip with external connecting terminal
03/22/2005US6870247 Interposer with a lateral recess in a slot to facilitate connection of intermediate conductive elements to bond pads of a semiconductor die with which the interposer is assembled
03/22/2005US6870242 Method for manufacturing and structure of semiconductor device with polysilicon definition structure
03/22/2005US6870241 High frequency switch circuit device
03/22/2005US6870240 Anti-fuse and method for writing information into the anti-fuse
03/22/2005US6870236 Integrated resistor network for multi-functional use in constant current or constant voltage operation of a pressure sensor
03/22/2005US6870233 Multi-bit ROM cell with bi-directional read and a method for making thereof
03/22/2005US6870231 Layouts for CMOS SRAM cells and devices
03/22/2005US6870230 Semiconductor device utilizing dummy features to form uniform sidewall structures
03/22/2005US6870228 System and method to reduce noise in a substrate
03/22/2005US6870227 Device for protecting against electrostatic discharge
03/22/2005US6870226 Semiconductor device and method of manufacturing same
03/22/2005US6870225 Transistor structure with thick recessed source/drain structures and fabrication process of same
03/22/2005US6870224 MOS transistor apparatus and method of manufacturing same
03/22/2005US6870223 High power semiconductor device having a Schottky barrier diode
03/22/2005US6870218 Integrated circuit structure with improved LDMOS design
03/22/2005US6870216 Stack gate with tip vertical memory and method for fabricating the same
03/22/2005US6870215 Semiconductor memory and its production process
03/22/2005US6870214 Method of fabricating flash EEPROM
03/22/2005US6870213 EEPROM device with substrate hot-electron injector for low-power
03/22/2005US6870212 Trench flash memory device and method of fabricating thereof
03/22/2005US6870211 Self-aligned array contact for memory cells
03/22/2005US6870210 Dual-sided capacitor
03/22/2005US6870209 CMOS pixel with dual gate PMOS
03/22/2005US6870208 Image sensor module
03/22/2005US6870205 Scalable hierarchical I/O line structure for a semiconductor memory device
03/22/2005US6870204 Heterojunction bipolar transistor containing at least one silicon carbide layer
03/22/2005US6870203 Field-effect semiconductor device and method for making the same
03/22/2005US6870200 Insulated gate type semiconductor device having a diffusion region contacting bottom and side portions of trenches
03/22/2005US6870199 Semiconductor device having an electrode overlaps a short carrier lifetime region
03/22/2005US6870189 Pinch-off type vertical junction field effect transistor and method of manufacturing the same
03/22/2005US6870188 LCD with increased pixel opening sizes
03/22/2005US6870187 Thin film transistor array panel and manufacturing method thereof
03/22/2005US6870181 Organic contact-enhancing layer for organic field effect transistors
03/22/2005US6870180 Organic polarizable gate transistor apparatus and method
03/22/2005US6870179 Increasing stress-enhanced drive current in a MOS transistor
03/22/2005US6870173 Electron-beam focusing apparatus and electron-beam projection lithography system employing the same
03/22/2005US6870171 Exposure apparatus
03/22/2005US6870170 Ion implant dose control
03/22/2005US6870169 Method and apparatus for analyzing composition of defects
03/22/2005US6870127 Chip scale marker and marking method
03/22/2005US6870126 Semiconductor device, annealing method, annealing apparatus and display apparatus
03/22/2005US6870125 Crystal layer separation method, laser irradiation method and method of fabricating devices using the same
03/22/2005US6869899 Lateral-only photoresist trimming for sub-80 nm gate stack
03/22/2005US6869898 Quartz glass jig for processing apparatus using plasma
03/22/2005US6869897 Manufacturing method for semiconductor substrate, and semiconductor device having a strained Si layer
03/22/2005US6869896 Plasma processes for depositing low dielectric constant films
03/22/2005US6869895 Method for adjusting capacitance of an on-chip capacitor
03/22/2005US6869894 Spin-on adhesive for temporary wafer coating and mounting to support wafer thinning and backside processing
03/22/2005US6869893 Laminate low K film
03/22/2005US6869892 Method of oxidizing work pieces and oxidation system
03/22/2005US6869891 Semiconductor device having groove and method of fabricating the same
03/22/2005US6869890 Processing apparatus to be sealed against workpiece
03/22/2005US6869889 Etching metal carbide films
03/22/2005US6869888 E-beam flood exposure of spin-on material to eliminate voids in vias
03/22/2005US6869887 Method for manufacturing thin film semiconductor device and method for forming resist pattern thereof
03/22/2005US6869886 Process for etching a metal layer system
03/22/2005US6869885 Method for a tungsten silicide etch
03/22/2005US6869884 Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
03/22/2005US6869882 Method of creating a photonic via using deposition
03/22/2005US6869880 In situ application of etch back for improved deposition into high-aspect-ratio features
03/22/2005US6869879 Method for forming conductive interconnects
03/22/2005US6869878 Method of forming a selective barrier layer using a sacrificial layer
03/22/2005US6869877 Integrated capacitors fabricated with conductive metal oxides
03/22/2005US6869876 Process for atomic layer deposition of metal films
03/22/2005US6869875 Method to achieve continuous hydrogen saturation in sparingly used electroless nickel plating process
03/22/2005US6869874 Method for fabricating contact plug with low contact resistance
03/22/2005US6869873 Copper silicide passivation for improved reliability
03/22/2005US6869872 Method of manufacturing a semiconductor memory device having a metal contact structure
03/22/2005US6869871 Method of forming metal line in semiconductor device including forming first and second zirconium films
03/22/2005US6869870 High performance system-on-chip discrete components using post passivation process
03/22/2005US6869868 Method of fabricating a MOSFET device with metal containing gate structures
03/22/2005US6869867 Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same wherein the silicide on gate is thicker than on source-drain
03/22/2005US6869866 Silicide proximity structures for CMOS device performance improvements
03/22/2005US6869865 Method of manufacturing semiconductor device
03/22/2005US6869864 Method for producing quantum dot silicate thin film for light emitting device
03/22/2005US6869863 Fabrication process of solar cell
03/22/2005US6869862 Method for improving a physical property defect value of a gate dielectric
03/22/2005US6869861 Back-side wafer singulation method
03/22/2005US6869860 Filling high aspect ratio isolation structures with polysilazane based material
03/22/2005US6869859 Semiconductor device and method of fabricating the same
03/22/2005US6869858 Shallow trench isolation planarized by wet etchback and chemical mechanical polishing
03/22/2005US6869857 Method to achieve STI planarization
03/22/2005US6869856 Process for manufacturing a semiconductor wafer integrating electronic devices including a structure for electromagnetic decoupling
03/22/2005US6869855 Method for making electrode pairs
03/22/2005US6869854 Diffused extrinsic base and method for fabrication
03/22/2005US6869853 Fabrication of a bipolar transistor using a sacrificial emitter
03/22/2005US6869852 Self-aligned raised extrinsic base bipolar transistor structure and method
03/22/2005US6869851 Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps
03/22/2005US6869850 Self-aligned contact structure with raised source and drain
03/22/2005US6869849 Semiconductor device and its manufacturing method
03/22/2005US6869848 Method of manufacturing flash memory device
03/22/2005US6869847 Semiconductor device manufacturing method thereof
1 ... 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 ... 6590