Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
01/2014
01/30/2014WO2013184850A3 Normally-off gallium nitride transistor with insulating gate and method of making same
01/30/2014WO2013171636A9 Three-dimensional modules for electronic integration
01/30/2014WO2013156568A3 Circuit arrangement for thermally conductive chip assembly and production method
01/30/2014WO2013114218A3 High-throughput continuous gas-phase synthesis of nanowires with tunable properties
01/30/2014WO2013016133A3 A one-component, dual-cure adhesive for use on electronics
01/30/2014US20140030897 Polishing composition and polishing method using the same
01/30/2014US20140030896 Etching method, and etching liquid to be used therein and method of producing a semiconductor substrate product using the same
01/30/2014US20140030895 Methods and system for generating a three-dimensional holographic mask
01/30/2014US20140030894 Methods of fabricating fine patterns and photomask sets used therein
01/30/2014US20140030893 Method for shrink and tune trench/via cd
01/30/2014US20140030892 Method for manufacturing silicon carbide substrate
01/30/2014US20140030891 Method of manufacturing semiconductor device and apparatus for manufacturing semiconductor device
01/30/2014US20140030890 Super-Self-Aligned Contacts and Method for Making the Same
01/30/2014US20140030889 Methods of improving tungsten contact resistance in small critical dimension features
01/30/2014US20140030888 Dishing-Free Gap-Filling with Multiple CMPs
01/30/2014US20140030887 Sputtering and Aligning Multiple Layers Having Different Boundaries
01/30/2014US20140030886 Method for forming copper wiring
01/30/2014US20140030885 Method for forming dual damascene opening
01/30/2014US20140030884 Method for fabricating semiconductor device including silicon-containing layer and metal-containing layer, and conductive structure of the same
01/30/2014US20140030883 Semiconductor device and method for fabricating the same
01/30/2014US20140030882 Manufacturing method of multi-trench termination structure for semiconductor device
01/30/2014US20140030881 Photoresist composition, thin film transistor array panel, and method of manufacturing the same
01/30/2014US20140030880 Method of Semiconductor Integrated Circuit Fabrication
01/30/2014US20140030879 Method of vapor-diffusing impurities
01/30/2014US20140030877 Process to dissolve the oxide layer in the peripheral ring of a structure of semiconductor-on-insulator type
01/30/2014US20140030876 Methods for fabricating high carrier mobility finfet structures
01/30/2014US20140030875 Method for forming compound epitaxial layer by chemical bonding and epitaxy product made by the same method
01/30/2014US20140030874 Method for manufacturing silicon carbide substrate
01/30/2014US20140030873 Method for fabricating patterned silicon nanowire array and silicon microstructure
01/30/2014US20140030872 Nano-structure manufacturing method using sacrificial etching mask
01/30/2014US20140030871 Trap Rich Layer with Through-Silicon-Vias in Semiconductor Devices
01/30/2014US20140030870 Sos substrate having low surface defect density
01/30/2014US20140030869 Self-aligned semiconductor trench structures
01/30/2014US20140030868 Deposit/etch for tapered oxide
01/30/2014US20140030867 Methods of fabricating a semiconductor device
01/30/2014US20140030866 Method and apparatus for preparing polysilazane on a semiconductor wafer
01/30/2014US20140030864 Method of eDRAM DT Strap Formation In FinFET Device Structure
01/30/2014US20140030863 Methods of forming capacitors
01/30/2014US20140030860 Manufacturing method of tunnel oxide of nor flash memory
01/30/2014US20140030859 Method of making a wire-based semiconductor device
01/30/2014US20140030858 Enhancement Mode III-Nitride Device
01/30/2014US20140030856 Three dimensional memory and methods of forming the same
01/30/2014US20140030855 Method of manufacturing flip chip package
01/30/2014US20140030854 High Voltage Cascoded III-Nitride Rectifier Package
01/30/2014US20140030853 Electrical connectivity for circuit applications
01/30/2014US20140030852 Semiconductor package with integrated interference shielding and method of manufacture thereof
01/30/2014US20140030850 Package substrate processing method
01/30/2014US20140030847 Bonding method using porosified surfaces for making stacked structures
01/30/2014US20140030840 Semiconductor device, solid-state imaging device, method for manufacturing semiconductor device, method for manufacturing solid-state imaging device, and electronic apparatus
01/30/2014US20140030839 Method of diffusing impurity-diffusing component and method of manufacturing solar cell
01/30/2014US20140030838 Charge sensors using inverted lateral bipolar junction transistors
01/30/2014US20140030837 Method of fabricating gallium nitride-based semiconductor device
01/30/2014US20140030836 Silicon Carbide Lamina
01/30/2014US20140030827 Underfill adhesion measurements at a microscopic scale
01/30/2014US20140030826 Polishing method
01/30/2014US20140030657 Manufacturing method of photomask, method for optical proximity correction, and manufacturing method of semiconductor device
01/30/2014US20140030621 Methods of operating fuel cells
01/30/2014US20140030533 Innovative top-coat approach for advanced device on-wafer particle performance
01/30/2014US20140030486 Chemistry compatible coating material for advanced device on-wafer particle performance
01/30/2014US20140030048 Workpiece transport device
01/30/2014US20140029352 Vertical memory with body connection
01/30/2014US20140029234 Reliable surface mount integrated power module
01/30/2014US20140029210 Diffusion barrier for surface mount modules
01/30/2014US20140029205 Band Pass Filter for 2.5D/3D Integrated Circuit Applications
01/30/2014US20140029181 Interlayer interconnects and associated techniques and configurations
01/30/2014US20140028990 Polarization-modulating element, illumination optical apparatus, exposure apparatus, and exposure method
01/30/2014US20140027933 Device and method for alignment of vertically stacked wafers and die
01/30/2014US20140027932 Manufacturing an underfill in a semiconductor chip package
01/30/2014US20140027931 Stack packages using reconstituted wafers
01/30/2014US20140027928 Semiconductor device having crack-resisting ring structure and manufacturing method thereof
01/30/2014US20140027927 Method for manufacturing a component having an electrical through-connection
01/30/2014US20140027926 Semiconductor package and method of fabricating the same
01/30/2014US20140027925 Through-holed interposer, packaging substrate, and methods of fabricating the same
01/30/2014US20140027924 Semiconductor devices including spacers on sidewalls of conductive lines and methods of manufacturing the same
01/30/2014US20140027923 Non-lithographic hole pattern formation
01/30/2014US20140027922 Via in substrate with deposited layer
01/30/2014US20140027920 Semiconductor device and method for manufacturing the same
01/30/2014US20140027918 Cross-coupling based design using diffusion contact structures
01/30/2014US20140027917 Non-lithographic line pattern formation
01/30/2014US20140027915 Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures
01/30/2014US20140027914 Protection of under-layer conductive pathway
01/30/2014US20140027910 Method for reducing wettability of interconnect material at corner interface and device incorporating same
01/30/2014US20140027909 Metallization of fluorocarbon-based dielectric for interconnects
01/30/2014US20140027908 Integrated Circuit Interconnects and Methods of Making Same
01/30/2014US20140027902 Repairing anomalous stiff pillar bumps
01/30/2014US20140027901 Package-on-package structures having buffer dams and methods for forming the same
01/30/2014US20140027900 Bump Structure for Yield Improvement
01/30/2014US20140027898 Multichip electronic packages and methods of manufacture
01/30/2014US20140027897 Semiconductor memory device and method of fabricating the same
01/30/2014US20140027896 Semiconductor device package with cap element
01/30/2014US20140027892 Electric Device Package Comprising a Laminate and Method of Making an Electric Device Package Comprising a Laminate
01/30/2014US20140027891 Semiconductor device and method for manufacturing semiconductor device
01/30/2014US20140027887 Wafer backside doping for thermal neutron shielding
01/30/2014US20140027886 Method of fabricating a device with a concentration gradient and the corresponding device
01/30/2014US20140027884 System and method for gas-phase sulfur passivation of a semiconductor surface
01/30/2014US20140027878 Self-aligned trench over fin
01/30/2014US20140027867 Packages and methods for 3d integration
01/30/2014US20140027864 Semiconductor devices and methods for manufacturing the same
01/30/2014US20140027863 Merged fin finfet with (100) sidewall surfaces and method of making same
01/30/2014US20140027860 Self-aligned 3-d epitaxial structures for mos device fabrication