Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2014
05/13/2014US8723274 Semiconductor device and method for fabricating the same
05/13/2014US8723270 Semiconductor memory device and fabrication process thereof
05/13/2014US8723267 Integrated circuit made out of SOI with transistors having distinct threshold voltages
05/13/2014US8723265 Semiconductor structure with dummy polysilicon lines
05/13/2014US8723260 Semiconductor radio frequency switch with body contact
05/13/2014US8723250 Integrated circuit devices including complex dielectric layers and related fabrication methods
05/13/2014US8723248 Nonvolatile semiconductor storage device
05/13/2014US8723247 Semiconductor memory device and method for manufacturing same
05/13/2014US8723237 Method for designing a semiconductor device including stress films
05/13/2014US8723236 FinFET device and method of manufacturing same
05/13/2014US8723234 Semiconductor device having a diode forming area formed between a field-effect transistor forming area and a source electrode bus wiring or pad
05/13/2014US8723229 Semiconductor device and method of manufacturing the device
05/13/2014US8723227 Heterojunction compound semiconductor protection clamps and methods of forming the same
05/13/2014US8723219 Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer
05/13/2014US8723185 Reducing wafer distortion through a high CTE layer
05/13/2014US8723182 Semiconductor device and method of manufacturing the same
05/13/2014US8723173 Semiconductor device, power circuit, and manufacturing method of semiconductor device
05/13/2014US8723172 Display device, thin film transistor array substrate and thin film transistor having oxide semiconductor
05/13/2014US8723154 Integration of an amorphous silicon resistive switching device
05/13/2014US8723027 Photovoltaic applications of non-conjugated conductive polymers
05/13/2014US8723026 Parallel coaxial molecular stack arrays
05/13/2014US8723019 Solar cell and method of manufacturing the same
05/13/2014US8722768 Liquid resin composition and semiconductor device
05/13/2014US8722549 Semiconductor device capable of reducing plasma induced damage and fabrication method thereof
05/13/2014US8722548 Structures and techniques for atomic layer deposition
05/13/2014US8722547 Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries
05/13/2014US8722546 Method for forming silicon-containing dielectric film by cyclic deposition with side wall coverage control
05/13/2014US8722545 Method of selectively deglazing P205
05/13/2014US8722544 Method of cleaning and micro-etching semiconductor wafers
05/13/2014US8722543 Composite hard mask with upper sacrificial dielectric layer for the patterning and etching of nanometer size MRAM devices
05/13/2014US8722542 Gas cluster ion beam process for opening conformal layer in a high aspect ratio contact via
05/13/2014US8722541 Double patterning method for semiconductor devices
05/13/2014US8722540 Controlling defects in thin wafer handling
05/13/2014US8722539 Process for through silicon via filling
05/13/2014US8722538 Method for forming contact window
05/13/2014US8722537 Multi-sacrificial layer and method
05/13/2014US8722536 Fabrication method for circuit substrate having post-fed die side power supply connections
05/13/2014US8722535 Pattern forming method, mold and data processing method
05/13/2014US8722534 Method for reducing wettability of interconnect material at corner interface and device incorporating same
05/13/2014US8722532 Semiconductor device and a method for manufacturing a semiconductor device
05/13/2014US8722531 Barrier layer for copper interconnect
05/13/2014US8722530 Method of making a die with recessed aluminum die pads
05/13/2014US8722529 Double solid metal pad with reduced area
05/13/2014US8722528 Die backside standoff structures for semiconductor devices
05/13/2014US8722527 Integrated circuit manufacturing method and integrated circuit
05/13/2014US8722526 Growing of gallium-nitrade layer on silicon substrate
05/13/2014US8722525 Multi-tiered semiconductor devices and associated methods
05/13/2014US8722524 Method for forming a semiconductor device including replacing material of dummy gate stacks with other conductive material
05/13/2014US8722522 Electro-static discharge protection device, semiconductor device, and method for manufacturing electro-static discharge protection device
05/13/2014US8722521 Method of laser irradiation, laser irradiation apparatus, and method of manufacturing a semiconductor device
05/13/2014US8722520 Method of fabricating a semiconductor device having an epitaxy region
05/13/2014US8722518 Methods for protecting patterned features during trench etch
05/13/2014US8722517 Dicing tape-integrated film for semiconductor back surface
05/13/2014US8722516 Laser processing method and method for manufacturing light-emitting device
05/13/2014US8722515 Process of treating defects during the bonding of wafers
05/13/2014US8722514 Semiconductor devices having insulating substrates and methods of formation thereof
05/13/2014US8722513 Semiconductor chip stack package and manufacturing method thereof
05/13/2014US8722512 Method of manufacturing semiconductor device with a dummy layer
05/13/2014US8722511 Reduced topography in isolation regions of a semiconductor device by applying a deposition/etch sequence prior to forming the interlayer dielectric
05/13/2014US8722510 Trench-filling method and film-forming system
05/13/2014US8722509 Method of forming trench isolation
05/13/2014US8722508 Low harmonic RF switch in SOI
05/13/2014US8722507 Method for forming identification marks on silicon carbide single crystal substrate, and silicon carbide single crystal substrate
05/13/2014US8722506 Production of high alignment marks and such alignment marks on a semiconductor wafer
05/13/2014US8722504 Interfacial layer for DRAM capacitor
05/13/2014US8722503 Capacitors and methods of forming
05/13/2014US8722502 Chip-stacked semiconductor device and manufacturing method thereof
05/13/2014US8722501 Method for manufacturing multi-gate transistor device
05/13/2014US8722500 Methods for fabricating integrated circuits having gate to active and gate to gate interconnects
05/13/2014US8722499 Method for fabricating a field effect device with weak junction capacitance
05/13/2014US8722496 Method for making embedded cost-efficient SONOS non-volatile memory
05/13/2014US8722495 Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
05/13/2014US8722494 Dual gate finFET devices
05/13/2014US8722493 Logic transistor and non-volatile memory cell integration
05/13/2014US8722492 Nanowire pin tunnel field effect devices
05/13/2014US8722491 Replacement metal gate semiconductor device formation using low resistivity metals
05/13/2014US8722490 Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling and device thus obtained
05/13/2014US8722489 Method of fabricating non-volatile memory device
05/13/2014US8722488 Method of fabricating semiconductor device
05/13/2014US8722487 Semiconductor device with an electrode including an aluminum-silicon film
05/13/2014US8722486 Enhancing deposition uniformity of a channel semiconductor alloy by forming a recess prior to the well implantation
05/13/2014US8722485 Integrated circuits having replacement gate structures and methods for fabricating the same
05/13/2014US8722484 High-K dielectric stack and method of fabricating same
05/13/2014US8722483 Method for manufacturing double-layer polysilicon gate
05/13/2014US8722482 Strained silicon carbide channel for electron mobility of NMOS
05/13/2014US8722481 Superior integrity of high-k metal gate stacks by preserving a resist material above end caps of gate electrode structures
05/13/2014US8722479 Method of protecting STI structures from erosion during processing operations
05/13/2014US8722478 Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications
05/13/2014US8722477 Cascoded high voltage junction field effect transistor
05/13/2014US8722476 Compound semiconductor device and manufacture process thereof
05/13/2014US8722475 Method and structure for high Q varactor
05/13/2014US8722474 Semiconductor device including stepped gate electrode and fabrication method thereof
05/13/2014US8722473 Semiconductor devices and methods of manufacture thereof
05/13/2014US8722472 Hybrid CMOS nanowire mesh device and FINFET device
05/13/2014US8722471 Method for forming a via contacting several levels of semiconductor layers
05/13/2014US8722470 CMOS with channel p-FinFET and channel n-FinFET having different crystalline orientations and parallel fins
05/13/2014US8722468 Semiconductor encapsulation method
05/13/2014US8722467 Method of using bonding ball array as height keeper and paste holder in semiconductor device package
05/13/2014US8722466 Semiconductor packaging and fabrication method using connecting plate for internal connection
05/13/2014US8722465 Method of assembling semiconductor device including insulating substrate and heat sink
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