Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2014
05/15/2014US20140134760 Devices and methods for embedding semiconductors in printed circuit boards
05/15/2014US20140134759 Method of forming a pattern
05/15/2014US20140134758 Techniques for matching spectra
05/15/2014US20140134757 Method to Form Multiple Trenches Utilizing a Grayscale Mask
05/15/2014US20140134756 Biomolecular recognition of crystal defects
05/15/2014US20140134755 Method and device for repairing open line defect in liquid crystal display array substrate
05/15/2014US20140133942 Substrate transfer system and substrate processing system
05/15/2014US20140132353 Amplifier circuit
05/15/2014US20140132302 Method for measuring potential induced degradation of at least one solar cell or of a photovoltaic panel as well as the use of same method in the production of solar cells and photovoltaic panels
05/15/2014US20140132117 Method of fabricating rare-earth doped piezoelectric material with various amounts of dopants and a selected c-axis orientation
05/15/2014US20140131900 Microelectronic assembly with thermally and electrically conductive underfill
05/15/2014US20140131899 Package for an integrated circuit
05/15/2014US20140131897 Warpage Control for Flexible Substrates
05/15/2014US20140131894 POP Structures with Air Gaps and Methods for Forming the Same
05/15/2014US20140131891 Semiconductor device and process for fabricating the same
05/15/2014US20140131888 Method for producing an electrical feedthrough in a substrate, and substrate having an electrical feedthrough
05/15/2014US20140131887 Package structure and method of forming the same
05/15/2014US20140131885 Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro
05/15/2014US20140131884 Through-Substrate via Formation with Improved Topography Control
05/15/2014US20140131883 Semiconductor structure and semiconductor fabricating process for the same
05/15/2014US20140131882 Through-silicon via structure with patterned surface, patterned sidewall and local isolation
05/15/2014US20140131881 Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
05/15/2014US20140131879 Design method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device
05/15/2014US20140131878 Semiconductor devices with enhanced electromigration performance
05/15/2014US20140131876 Method for dicing a semiconductor wafer having through silicon vias and resultant structures
05/15/2014US20140131875 Z-connection using electroless plating
05/15/2014US20140131874 Semiconductor apparatus, electronic device, and method of manufacturing semiconductor apparatus
05/15/2014US20140131872 Copper etching integration scheme
05/15/2014US20140131868 Systems and Methods for Producing Low Work Function Electrodes
05/15/2014US20140131866 Trace routing within a semiconductor package substrate
05/15/2014US20140131865 Structure and Method for Bump to Landing Trace Ratio
05/15/2014US20140131859 Solder fatigue arrest for wafer level package
05/15/2014US20140131856 Semiconductor device and manufacturing method thereof
05/15/2014US20140131855 Thermocompression for semiconductor chip assembly
05/15/2014US20140131854 Multi-chip module connection by way of bridging blocks
05/15/2014US20140131853 Electronic component, method of manufacturing same, composite module including electronic component, and method of manufacturing same
05/15/2014US20140131851 Structure for microelectronic packaging with terminals on dielectric mass
05/15/2014US20140131848 Land structure for semiconductor package and method therefor
05/15/2014US20140131846 Power semiconductor module and method of manufacturing the same
05/15/2014US20140131842 Axial semiconductor package
05/15/2014US20140131841 Metal pad structure over tsv to reduce shorting of upper metal layer
05/15/2014US20140131840 Wafer and method of manufacturing the same
05/15/2014US20140131839 Etching Method Using Block-Copolymers
05/15/2014US20140131837 Gan vertical bipolar transistor
05/15/2014US20140131832 Method for manufacturing semiconductor layout pattern, method for manufacturing semiconductor device, and semiconductor device
05/15/2014US20140131831 Integrated ciruit including an fin-based diode and methods of its fabrication
05/15/2014US20140131830 Solid state devices having fine pitch structures
05/15/2014US20140131813 Cell Layout for SRAM FinFET Transistors
05/15/2014US20140131812 Source and Drain Dislocation Fabrication in FinFETs
05/15/2014US20140131809 Replacement metal gate structure for cmos device
05/15/2014US20140131808 Replacement metal gate structure for cmos device
05/15/2014US20140131806 Semiconductor devices and methods for manufacturing the same
05/15/2014US20140131804 Semiconductor structure
05/15/2014US20140131800 Compensation for a charge in a silicon substrate
05/15/2014US20140131782 Semiconductor device having diffusion barrier to reduce back channel leakage
05/15/2014US20140131777 Integrated circuits and methods for fabricating integrated circuits with salicide contacts on non-planar source/drain regions
05/15/2014US20140131776 Fin Recess Last Process for FinFET Fabrication
05/15/2014US20140131775 VERTICAL GaN JFET WITH LOW GATE-DRAIN CAPACITANCE AND HIGH GATE-SOURCE CAPACITANCE
05/15/2014US20140131771 Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
05/15/2014US20140131752 Phosphor layer-covered optical semiconductor element, producing method thereof, optical semiconductor device, and producing method thereof
05/15/2014US20140131722 Dual phase gallium nitride material formation on (100) silicon
05/15/2014US20140131720 Composite layer stacking for enhancement mode transistor
05/15/2014US20140131708 Semiconductor device including an asymmetric feature, and method of making the same
05/15/2014US20140131707 Method and device for detecting termination of etching
05/15/2014US20140131696 Method for producing field effect transistor, field effect transistor, display device, image sensor, and x-ray sensor
05/15/2014US20140131662 Graphene Formation on Dielectrics and Electronic Devices Formed Therefrom
05/15/2014US20140131659 Gallium Nitride Devices With Aluminum Nitride Intermediate Layer
05/15/2014US20140131315 Method of processing a material-specimen
05/15/2014US20140131086 Lead Frame Strip with Half (1/2) Thickness Pull Out Tab
05/15/2014US20140131005 Temperature control system for electrostatic chucks and electrostatic chuck for same
05/15/2014US20140130981 Apparatus for non-chemical, non-optical edge bead removal
05/15/2014US20140130962 Thin wafer handling method
05/15/2014US20140130825 Substrate cleaning method and system using atmospheric pressure atomic oxygen
05/15/2014US20140130743 Film forming apparatus
05/15/2014US20140130732 Wafer holder cleaning apparatus and film deposition system including the same
05/15/2014US20140130731 Use of surfactants to control island size and density
05/15/2014US20140130340 Die-positioning device, die-positioning system having the same, and die-positioning method of led display board
05/15/2014DE112012003260T5 Substrat, Halbleitervorrichtung und Verfahren zur Herstellung derselben Substrate, semiconductor device and method of manufacturing the same
05/15/2014DE112012003258T5 Siliciumcarbid-Halbleiterbauelement Silicon carbide semiconductor device
05/15/2014DE112012002504T5 Offset reduzierende Widerstandsschaltung Offset reducing resistance circuit
05/15/2014DE112012002299T5 Verfahren zum Herstellen eines Siliziumkarbidsubstrates A method for producing a Siliziumkarbidsubstrates
05/15/2014DE112012000272B4 Verfahren zum bilden von silicid, germanid oder germanosilicid in strukturen, die einen nanodraht aufweisen Methods of forming silicide or germanide germanosilicid in structures having a nano wire
05/15/2014DE112011100788B4 Elektrisches Bauelement, insbesondere CMOS-Bauelement, und Verfahren zum Herstellen eines Halbleiterbauelements Electrical component, in particular CMOS device, and method for manufacturing a semiconductor device
05/15/2014DE112010003269B4 Struktur mit kopplung zwischen strukturen mit sublithographischem rasterabstand und strukturen mit lithographischem rasterabstand und verfahren zur herstellung der struktur Structure with coupling between pitch with sublithographischem structures and structures with lithographic pitch and method for making the structure
05/15/2014DE112007001605B4 Zinkoxiddünnfilm vom p-Typ und Verfahren zur Ausbildung desselben und lichtemittierendes Element Zinc oxide thin film of the same p-type and method of forming and emitting element
05/15/2014DE102013223249A1 Inhomogene Leistungshalbleiterbauelemente Inhomogeneous power semiconductor components
05/15/2014DE102013218238A1 Verfahren zur herstellung eines steuerbaren halbleiterbauelements Process for the preparation of a controllable semiconductor component
05/15/2014DE102013217565A1 Verfahren zum Herstellen einer Halbleitervorrichtung A method of manufacturing a semiconductor device
05/15/2014DE102013207502A1 Optical system for wafer and mask inspection plant, has polarizing elements which are designed such that polarization distribution set to micro-structured element is not changed by changing operating wavelength
05/15/2014DE102013112361A1 Halbleitervorrichtung mit metallgefüllter Nut in einer Polysilicium-Gateelektrode A semiconductor device having metal-filled groove in a polysilicon gate electrode
05/15/2014DE102013112137A1 Verfahren zum Verarbeiten eines Dies This method of processing a
05/15/2014DE102013109131A1 Halbleitervorrichtung mit linienförmigem Graben zum Definieren eines aktiven Bereichs sowie Verfahren zur Herstellung derselben A semiconductor device with a linear trench for defining an active region and to processes for the preparation thereof
05/15/2014DE102013104983A1 Zellen-Layout für SRAM-FinFET-Transistoren Cell layout for SRAM-FinFET transistors
05/15/2014DE102013102156A1 Verbundschichtstapelung für Enhancement Mode-Transistor Composite layer stacking for enhancement mode transistor
05/15/2014DE102013101191A1 Widerstandsvariable Speicherstruktur und Verfahren zur Ausbildung Dieser Resistance variable memory structure and method for forming this
05/15/2014DE102013100700B3 Method of manufacturing semiconductor device module, involves inserting terminal free ends into contact holes of a board and introducing adjusting device relative to carrier in different relative positions by sliding board on terminals
05/15/2014DE102012220909A1 Verfahren zum Vereinzeln von Bereichen einer Halbleiterschicht A method for separating regions of a semiconductor layer
05/15/2014DE102012220416A1 Fotoempfänger mit einer Vielzahl von Fotozellen und Durchkontaktierungen sowie Verfahren zu dessen Herstellung Photoreceiver having a plurality of photo cells, and vias, as well as method for its preparation
05/15/2014DE102012214085A1 Halbleiterscheibe aus einkristallinem Silizium und Verfahren zu deren Herstellung Semiconductor wafer made of monocrystalline silicon, and process for their preparation
05/15/2014DE102012207913B4 Verfahren zum Herstellen einer Fin-FET-Einheit A method of manufacturing a fin-FET unit
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