Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2014
09/18/2014US20140264898 3-D IC Device with Enhanced Contact Area
09/18/2014US20140264897 Damascene conductor for a 3d device
09/18/2014US20140264896 Structure and Method for a Low-K Dielectric with Pillar-Type Air-Gaps
09/18/2014US20140264895 Semiconductor Devices and Methods of Manufacture Thereof
09/18/2014US20140264894 System and method for arbitrary metal spacing for self-aligned double patterning
09/18/2014US20140264893 Pitch-halving integrated circuit process and integrated circuit structure made thereby
09/18/2014US20140264891 Forming fence conductors in an integrated circuit
09/18/2014US20140264889 Semiconductor device channels
09/18/2014US20140264887 Oriented crystal nanowire interconnects
09/18/2014US20140264886 Forming Fence Conductors Using Spacer Pattern Transfer
09/18/2014US20140264885 Apparatus and Method for Wafer Separation
09/18/2014US20140264884 WLCSP Interconnect Apparatus and Method
09/18/2014US20140264882 Forming Fence Conductors Using Spacer Etched Trenches
09/18/2014US20140264881 Methods and structures to facilitate through-silicon vias
09/18/2014US20140264880 Interconnect structure and method of forming the same
09/18/2014US20140264875 Semiconductor device and manufacturing method thereof
09/18/2014US20140264874 Electro-Migration Barrier for Cu Interconnect
09/18/2014US20140264873 Interconnection Structure And Method For Semiconductor Device
09/18/2014US20140264872 Metal Capping Layer for Interconnect Applications
09/18/2014US20140264871 Method to Increase Interconnect Reliability
09/18/2014US20140264870 Method of back-end-of-line (beol) fabrication, and devices formed by the method
09/18/2014US20140264868 Wafer-level die attach metallization
09/18/2014US20140264867 Method of forming hybrid diffusion barrier layer and semiconductor device thereof
09/18/2014US20140264866 Chemical direct pattern plating interconnect metallization and metal structure produced by the same
09/18/2014US20140264865 Semiconductor device and manufacturing method thereof
09/18/2014US20140264864 Integrated circuit structure and formation
09/18/2014US20140264863 Conductive Line System and Process
09/18/2014US20140264861 Sputter etch processing for heavy metal patterning in integrated circuits
09/18/2014US20140264860 Rectifier diode
09/18/2014US20140264859 Packaging Devices and Methods of Manufacture Thereof
09/18/2014US20140264857 Package-on-Package with Via on Pad Connections
09/18/2014US20140264850 Semiconductor Device and Method of Forming a Dual UBM Structure for Lead Free Bump Connections
09/18/2014US20140264846 Packaging Devices, Methods of Manufacture Thereof, and Packaging Methods
09/18/2014US20140264844 Semiconductor device having a die and through substrate-via
09/18/2014US20140264839 Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices
09/18/2014US20140264836 System-in-package with interposer pitch adapter
09/18/2014US20140264835 Semiconductor packages and methods of packaging semiconductor devices
09/18/2014US20140264831 Chip arrangement and a method for manufacturing a chip arrangement
09/18/2014US20140264829 Electronic assembly with copper pillar attach substrate
09/18/2014US20140264827 Methods of forming wafer level underfill materials and structures formed thereby
09/18/2014US20140264826 Semiconductor device and semiconductor device fabrication method
09/18/2014US20140264825 Ultra-Low Resistivity Contacts
09/18/2014US20140264823 Systems and Methods for Fabricating Semiconductor Devices Having Larger Die Dimensions
09/18/2014US20140264822 Thermosetting resin compositions with low coefficient of thermal expansion
09/18/2014US20140264817 Semiconductor Device and Method of Using Partial Wafer Singulation for Improved Wafer Level Embedded System in Package
09/18/2014US20140264816 Semiconductor package structure
09/18/2014US20140264813 Semiconductor Device Package and Method
09/18/2014US20140264810 Packages with Molding Material Forming Steps
09/18/2014US20140264808 Chip arrangements, chip packages, and a method for manufacturing a chip arrangement
09/18/2014US20140264807 Semiconductor device
09/18/2014US20140264805 Semiconductor Package And Fabrication Method Thereof
09/18/2014US20140264803 Package device including an opening in a flexible substrate and methods of forming the same
09/18/2014US20140264802 Semiconductor Device with Thick Bottom Metal and Preparation Method Thereof
09/18/2014US20140264794 Low cte interposer without tsv structure
09/18/2014US20140264792 Semiconductor packages and methods of packaging semiconductor devices
09/18/2014US20140264785 Chip package and method for forming the same
09/18/2014US20140264784 Metal Shielding on Die Level
09/18/2014US20140264782 Formation of a high aspect ratio contact hole
09/18/2014US20140264781 Passivation layer for harsh environments and methods of fabrication thereof
09/18/2014US20140264780 Adhesion layer to minimize dielectric constant increase with good adhesion strength in a pecvd process
09/18/2014US20140264779 Metal Deposition on Substrates
09/18/2014US20140264778 Precursor composition for deposition of silicon dioxide film and method for fabricating semiconductor device using the same
09/18/2014US20140264777 Nanocrystalline Diamond Three-Dimensional Films in Patterned Semiconductor Substrates
09/18/2014US20140264776 Semiconductor Wafer With A LayerOf AlzGa1-zN and Process For Producing It
09/18/2014US20140264775 Method and system for transient voltage suppression
09/18/2014US20140264774 Wafer and film coating method of using the same
09/18/2014US20140264772 Shielding for Through-Silicon-Via
09/18/2014US20140264770 Method of forming through substrate vias (tsvs) and singulating and releasing die having the tsvs from a mechanical support substrate
09/18/2014US20140264769 Packaging mechanisms for dies with different sizes of connectors
09/18/2014US20140264768 Die Preparation for Wafer-Level Chip Scale Package (WLCSP)
09/18/2014US20140264767 Wafer, Integrated Circuit Chip and Method for Manufacturing an Integrated Circuit Chip
09/18/2014US20140264766 System and Method for Film Stress Release
09/18/2014US20140264763 Engineered substrates for semiconductor epitaxy and methods of fabricating the same
09/18/2014US20140264761 Semiconductor devices and methods of making the same
09/18/2014US20140264759 Stacked wafer with coolant channels
09/18/2014US20140264758 Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processes
09/18/2014US20140264757 Metal structures and methods of using same for transporting or gettering materials disposed within semiconductor substrates
09/18/2014US20140264755 Strained silicon nfet and silicon germanium pfet on same wafer
09/18/2014US20140264754 Methods of forming doped elements and related semiconductor device structures
09/18/2014US20140264753 Novel Structure of W-Resistor
09/18/2014US20140264739 Methods of forming under device interconnect structures
09/18/2014US20140264734 Inductor With Magnetic Material
09/18/2014US20140264733 Device with integrated passive component
09/18/2014US20140264727 Semiconductor devices and methods of manufacturing the same
09/18/2014US20140264726 Structure and method for protected periphery semiconductor device
09/18/2014US20140264725 Silicon recess etch and epitaxial deposit for shallow trench isolation (sti)
09/18/2014US20140264724 Deep trench isolation
09/18/2014US20140264721 Isolation structure in a semiconductor device processes and structures
09/18/2014US20140264720 Method and Structure for Nitrogen-Doped Shallow-Trench Isolation Dielectric
09/18/2014US20140264719 Varied STI Liners for Isolation Structures in Image Sensing Devices
09/18/2014US20140264717 Method of Fabricating a FinFET Device
09/18/2014US20140264716 Semiconductor wafer, semiconductor process and semiconductor package
09/18/2014US20140264713 Gate contact for a semiconductor device and methods of fabrication thereof
09/18/2014US20140264709 Interconnect Structure for Connecting Dies and Methods of Forming the Same
09/18/2014US20140264682 Interconnect Sructure for Stacked Device and Method
09/18/2014US20140264678 Packaging for an electronic device
09/18/2014US20140264677 Chip Package with Isolated Pin, Isolated Pad or Isolated Chip Carrier and Method of Making the Same
09/18/2014US20140264635 RF Switch on High Resistive Substrate
09/18/2014US20140264631 Methods of forming alignment marks and overlay marks on integrated circuit products employing finfet devices and the resulting alignment/overlay mark
09/18/2014US20140264629 Local interconnect structures for high density
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