Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2014
09/18/2014US20140273343 Method for manufacturing semiconductor device
09/18/2014US20140273341 Methods for Forming Back-Channel-Etch Devices with Copper-Based Electrodes
09/18/2014US20140273328 Semiconductor element producing method
09/18/2014US20140273326 Methods for improving solar cell lifetime and efficiency
09/18/2014US20140273314 High Productivity Combinatorial Workflow to Screen and Design Chalcogenide Materials as Non Volatile Memory Current Selector
09/18/2014US20140273313 Method and apparatus providing inline photoluminescence analysis of a photovoltaic device
09/18/2014US20140273312 Pin hole evaluation method of dielectric films for metal oxide semiconductor tft
09/18/2014US20140273311 Optical Absorbers
09/18/2014US20140273310 Monitoring pattern for devices
09/18/2014US20140273309 Controlling Radical Lifetimes in a Remote Plasma Chamber
09/18/2014US20140273308 Method of measuring surface properties of polishing pad
09/18/2014US20140273307 Method and Apparatus for Semiconductor Testing at Low Temperature
09/18/2014US20140273306 Methods for fabricating integrated circuits including multi-patterning of masks for extreme ultraviolet lithography
09/18/2014US20140273304 Methods for reducing etch nonuniformity in the presence of a weak magnetic field in an inductively coupled plasma reactor
09/18/2014US20140273303 System and Method for an Etch Process with Silicon Concentration Control
09/18/2014US20140273302 Fine Temperature Controllable Wafer Heating System
09/18/2014US20140273301 Moveable and adjustable gas injectors for an etching chamber
09/18/2014US20140273300 Method for Forming ReRAM Chips Operating at Low Operating Temperatures
09/18/2014US20140273299 Systems and methods for fabricating semiconductor device structures using different metrology tools
09/18/2014US20140273298 Techniques for Quantifying Fin-Thickness Variation in FINFET Technology
09/18/2014US20140273297 Embedded test structure for trimming process control
09/18/2014US20140273296 Metric for recognizing correct library spectrum
09/18/2014US20140273295 Optical Control Of Multi-Stage Thin Film Solar Cell Production
09/18/2014US20140273294 System and Method for Forming a Semiconductor Device
09/18/2014US20140273293 Portable Wireless Sensor
09/18/2014US20140273292 Methods of forming silicon nitride spacers
09/18/2014US20140273291 Wafer Strength by Control of Uniformity of Edge Bulk Micro Defects
09/18/2014US20140273290 Solvent anneal processing for directed-self assembly applications
09/18/2014US20140272459 Corrosion resistant aluminum coating on plasma chamber components
09/18/2014US20140272421 Member for semiconductor manufacturing apparatuses
09/18/2014US20140272401 Adhesive film having good machinability for protecting the surface of a semiconductor wafer
09/18/2014US20140272341 Thermal treated sandwich structure layer to improve adhesive strength
09/18/2014US20140271097 Processing systems and methods for halide scavenging
09/18/2014US20140271086 Workpiece flipping mechanism for space-constrained environment
09/18/2014US20140271085 Substrate position aligner
09/18/2014US20140271057 Temperature control systems and methods for small batch substrate handling systems
09/18/2014US20140271055 Substrate deposition systems, robot transfer apparatus, and methods for electronic device manufacturing
09/18/2014US20140271054 Multi-position batch load lock apparatus and systems and methods including same
09/18/2014US20140271053 Pressure-controlled wafer carrier and wafer transport system
09/18/2014US20140271052 Substrate transfer device for substrate processing system
09/18/2014US20140271051 Substrate processing apparatus and substrate processing method
09/18/2014US20140271050 Wafer handling systems and methods
09/18/2014US20140271049 Vacuum processing apparatus and operating method thereof
09/18/2014US20140271048 High Throughput, Low Volume Clamshell Load Lock
09/18/2014US20140270736 Edge ring for a thermal processing chamber
09/18/2014US20140270735 High density solid state light source array
09/18/2014US20140270732 Heating lamp assembly
09/18/2014US20140270731 Thermal management apparatus for solid state light source arrays
09/18/2014US20140270057 X-ray sensor and signal processing assembly for an x-ray computed tomography machine
09/18/2014US20140269826 In-situ temperature measurement in a noisy environment
09/18/2014US20140269005 Electronic devices having semiconductor memory units and method for fabricating the same
09/18/2014US20140268619 Method of Manufacturing Substrate for Chip Packages and Method of Manufacturing Chip Package
09/18/2014US20140268614 Coupled vias for channel cross-talk reduction
09/18/2014US20140268609 Support structure for integrated circuitry
09/18/2014US20140268479 Substrate support chuck cooling for deposition chamber
09/18/2014US20140266494 Integration of a replica circuit and a transformer above a dielectric substrate
09/18/2014US20140266403 Low Loss Electronic Devices Having Increased Doping for Reduced Resistance and Methods of Forming the Same
09/18/2014US20140266284 Isolation testing of semiconductor devices
09/18/2014US20140266220 Detection of electroplating bath contamination
09/18/2014US20140265846 Scalable and uniformity controllable diffusion plasma source
09/18/2014US20140265394 Composite end effectors
09/18/2014US20140265101 Minimal contact edge ring for rapid thermal processing
09/18/2014US20140265093 Workpiece support structure with four degree of freedom air bearing for high vacuum systems
09/18/2014US20140265091 Susceptors for enhanced process uniformity and reduced substrate slippage
09/18/2014US20140265090 Substrate support bushing
09/18/2014US20140265089 Substrate support with advanced edge control provisions
09/18/2014US20140264961 Invisible Dummy Features and Method for Forming the Same
09/18/2014US20140264960 Encapsulation of advanced devices using novel pecvd and ald schemes
09/18/2014US20140264958 Semiconductor package, fabrication method thereof and molding compound
09/18/2014US20140264956 Sealant laminated composite, sealed semiconductor devices mounting substrate, sealed semiconductor devices forming wafer, semiconductor apparatus, and method for manufacturing semiconductor apparatus
09/18/2014US20140264955 Electronic device with an interlocking mold package
09/18/2014US20140264954 Passivation and warpage correction by nitride film for molded wafers
09/18/2014US20140264953 Wiring structures, methods of manufacturing the same, and methods of manufacturing semiconductor devices having the same
09/18/2014US20140264947 Interconnect Apparatus and Method
09/18/2014US20140264945 Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
09/18/2014US20140264937 Through-Silicon Vias and Interposers Formed by Metal-Catalyzed Wet Etching
09/18/2014US20140264935 Semiconductor device manufacturing method and semiconductor mounting substrate
09/18/2014US20140264934 Interlayer conductor structure and method
09/18/2014US20140264933 Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method
09/18/2014US20140264932 Patterning Approach to Reduce Via to Via Minimum Spacing
09/18/2014US20140264931 Stress Tuning for Reducing Wafer Warpage
09/18/2014US20140264930 Fan-Out Interconnect Structure and Method for Forming Same
09/18/2014US20140264929 Interconnect Structure for Stacked Device
09/18/2014US20140264928 Semiconductor package and fabrication method thereof
09/18/2014US20140264927 Single Mask Package Apparatus and Method
09/18/2014US20140264926 Method and Apparatus for Back End of Line Semiconductor Device Processing
09/18/2014US20140264925 Interlayer conductor and method for forming
09/18/2014US20140264924 Apparatus and method for mitigating dynamic ir voltage drop and electromigration affects
09/18/2014US20140264923 Interconnect structure with kinked profile
09/18/2014US20140264922 Semiconductor structure
09/18/2014US20140264921 Through-silicon via with sidewall air gap
09/18/2014US20140264920 Metal Cap Apparatus and Method
09/18/2014US20140264917 A Semiconductor Device with a Through-Silicon Via and a Method for Making the Same
09/18/2014US20140264914 Chip package-in-package and method thereof
09/18/2014US20140264911 Through silicon vias
09/18/2014US20140264908 Dual damascene gap filling process
09/18/2014US20140264905 Semiconductor Device and Method of Forming WLCSP with Semiconductor Die Embedded within Interconnect Structure
09/18/2014US20140264904 Unified pcb design for ssd applications, various density configurations, and direct nand access
09/18/2014US20140264903 Interconnect structure and method of forming the same
09/18/2014US20140264902 Novel Patterning Approach for Improved Via Landing Profile
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