Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
04/2008
04/09/2008CN100380518C Method for generating solid memory address configuration
04/08/2008US7356654 Flexible multi-area memory and electronic device using the same
04/08/2008US7355922 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
04/08/2008US7355921 Device in a memory circuit for definition of waiting times
04/08/2008US7355920 Write latency tracking using a delay lock loop in a synchronous DRAM
04/08/2008US7355918 Semiconductor memory device and refresh method thereof
04/08/2008US7355875 Nonvolatile semiconductor memory device having capacitor arranged between power supplies to prevent voltage fluctuation
04/03/2008US20080080298 Memory Data Transfer
04/03/2008US20080080297 Self-timed memory having common timing control circuit and method therefor
04/03/2008US20080080296 Wordline driving circuit and method for semiconductor memory
04/03/2008US20080080295 Embedded semiconductor memory device having self-timing control sense amplifier
04/03/2008US20080080294 Semiconductor memory device
04/03/2008US20080080293 Semiconductor memory apparatus having column decoder for low power consumption
04/03/2008US20080080292 Control component for controlling a semiconductor memory component in a semiconductor memory module
04/03/2008US20080080291 Interleaved input signal path for multiplexed input
04/03/2008US20080080286 Semiconductor memory device with partial refresh function
04/03/2008US20080080272 Semiconductor memory device and method for driving the same
04/03/2008US20080080265 Semiconductor memory and method for testing semiconductor memories
04/03/2008US20080080263 Semiconductor memory device and method for operating the same
04/03/2008US20080080256 Delay circuit for controlling a pre-charging time of bit lines of a memory cell array
04/03/2008DE102004022326B4 Verfahren zum Testen eines integrierten Halbleiterspeichers A method for testing an integrated semiconductor memory,
04/02/2008EP1906409A2 Semiconductor memory and system
04/02/2008EP1905042A2 Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations
04/02/2008CN101154435A Semiconductor memory and system
04/02/2008CN100378863C Circuit and method for addressing and reading crossover point diode storage array
04/02/2008CN100378704C Method and apparatus for optimizing timing for a multi-drop bus
04/01/2008USRE40205 Semiconductor device and timing control circuit
04/01/2008US7353356 High speed, low current consumption FIFO circuit
04/01/2008US7353325 Wear leveling techniques for flash EEPROM systems
04/01/2008US7352650 External clock synchronization semiconductor memory device and method for controlling same
04/01/2008US7352649 High speed array pipeline architecture
04/01/2008US7352648 Semiconductor memory
04/01/2008US7352647 Reduced power usage in a memory for a programmable logic device
04/01/2008US7352646 Semiconductor memory device and method of arranging a decoupling capacitor thereof
04/01/2008US7352621 Method for enhanced block management
04/01/2008US7352612 Method for operating a data storage apparatus employing passive matrix addressing
04/01/2008US7352604 Memory and driving method of the same
04/01/2008US7352603 Apparatus and methods for optically-coupled memory systems
04/01/2008US7352026 EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same
04/01/2008CA2467844C Method employed by a base station for transferring data
03/2008
03/27/2008US20080074943 Semiconductor memory device and method of controlling timing
03/27/2008US20080074942 Semiconductor memory and system
03/27/2008US20080074936 Read operation of multi-port memory device
03/27/2008US20080074934 Detection of row-to-row shorts and other row decode defects in memory devices
03/27/2008DE102007016603A1 Vorrichtung und darauf bezogenes Verfahren zum Steuern eines Switch-Moduls in einem Speicher durch Erfassen einer Betriebsfrequenz eines spezifischen Signals in einem Speicher The apparatus and related method for controlling a switch module in a memory by sensing an operating frequency of a specific signal in a memory
03/27/2008DE102004045903B4 Schaltungsanordnung und Verfahren zum Schalten von Hochspannungssignalen mit Niederspannungssignalen Circuit arrangement and method for the switching of high-voltage signals with low voltage signals
03/27/2008DE10041688B4 Integrierter Speicher mit Speicherzellen in mehreren Speicherzellenblöcken und Verfahren zum Betrieb eines solchen Speichers Integrated memory having memory cells in a plurality of memory cell blocks and method for operating such a memory,
03/26/2008CN101149964A Semiconductor memory device
03/26/2008CN100377259C Bidirectional shift register and display device incorporating same
03/26/2008CN100377256C Multi-port memory unit structure
03/26/2008CN100377197C Display driver, display device and driving method
03/25/2008US7350132 Nanoscale interconnection interface
03/25/2008US7350092 Data synchronization arrangement
03/25/2008US7349290 Semiconductor memory device
03/25/2008US7349288 Ultra high-speed Nor-type LSDL/Domino combined address decoder
03/25/2008US7349287 Address decoder, storage device, processor device, and address decoding method for the storage device
03/25/2008US7349286 Memory component and addressing of memory cells
03/25/2008US7349285 Dual port memory unit using a single port memory core
03/25/2008US7349284 Memory array with staged output
03/25/2008US7349279 Memory Device Having a Configurable Oscillator for Refresh Operation
03/25/2008US7349270 Semiconductor memory with wordline timing
03/25/2008US7349246 Initial firing method and phase change memory device for performing firing effectively
03/20/2008WO2008031217A1 Flash multi-level threshold distribution scheme
03/20/2008US20080068917 Controller for controlling a memory component in a semiconductor memory module
03/20/2008US20080068909 Semiconductor device
03/20/2008US20080068906 Method and apparatus for testing a memory device
03/20/2008CA2659872A1 Flash multi-level threshold distribution scheme
03/19/2008EP1342243B1 Memory device and method for the operation of the same
03/19/2008CN101147396A Processing a data array with a meandering scanning order using a circular buffer memory
03/18/2008US7346818 Method and apparatus for redundant location addressing using data compression
03/18/2008US7346750 Memory interleave system
03/18/2008US7345950 Synchronous semiconductor memory device
03/18/2008US7345949 Synchronous semiconductor memory device
03/18/2008US7345948 Clock circuit for semiconductor memories
03/18/2008US7345947 Memory array leakage reduction circuit and method
03/18/2008US7345946 Dual-voltage wordline drive circuit with two stage discharge
03/18/2008US7345945 Line driver circuit for a semiconductor memory device
03/18/2008US7345919 Semiconductor device that enables simultaneous read and write/read operation
03/13/2008WO2008031109A2 System and method for encrypting data
03/13/2008WO2007114858A3 Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent
03/13/2008WO2007081642A3 Flash devicewith shared word lines and manufacturing methods thereof
03/13/2008US20080062810 Apparatus and method for controlling clock signal in semiconductor memory device
03/13/2008US20080062809 Semiconductor memory apparatus
03/13/2008US20080062808 Semiconductor device
03/13/2008US20080062807 Multi-column addressing mode memory system including an integrated circuit memory device
03/13/2008US20080062806 Phase change memory comprising a low-voltage column decoder
03/13/2008US20080062805 Semiconductor storage device
03/13/2008US20080062804 Segmented search line circuit device for content addressable memory
03/13/2008US20080062803 System and method for encrypting data
03/13/2008US20080062792 Memory device and method for precharging a memory device
03/13/2008US20080062784 Semiconductor memory
03/13/2008US20080062779 Semiconductor integrated circuit
03/13/2008US20080062772 Data output circuit for semiconductor memory device
03/13/2008US20080062752 Phase change memory erasable and programmable by a row decoder
03/13/2008US20080062735 Nanoscale wire coding for stochastic assembly
03/12/2008EP1425753B1 Memory circuit
03/12/2008CN101140796A 半导体装置 Semiconductor device
03/11/2008USRE40147 Memory card device including a clock generator
03/11/2008US7342846 Address decoding systems and methods
03/06/2008WO2007136704A3 Nand system with a data write frequency greater than a command-and-address-load frequency
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