| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 02/08/2012 | EP1819048B1 Semiconductor device employing dynamic circuit |
| 02/07/2012 | US8112700 Nanoscale interconnection interface |
| 02/07/2012 | US8112608 Variable-width memory |
| 02/07/2012 | US8111580 Multi-phase duty-cycle corrected clock signal generator and memory having same |
| 02/07/2012 | US8111579 Circuits and methods for reducing minimum supply for register file cells |
| 02/07/2012 | US8111578 Memory devices having redundant arrays for repair |
| 02/07/2012 | US8111543 Semiconductor memory device |
| 02/07/2012 | US8111537 Semiconductor memory |
| 02/07/2012 | US8111534 Rank select using a global select pin |
| 02/02/2012 | WO2011156069A3 Memory arrays |
| 02/02/2012 | US20120030531 Safe Memory Storage By Internal Operation Verification |
| 02/02/2012 | US20120026821 Semiconductor device |
| 02/02/2012 | US20120026806 Data input circuit |
| 02/01/2012 | CN101127236B 存储单元电路 Memory cell circuit |
| 01/31/2012 | US8107315 Double data rate memory device having data selection circuit and data paths |
| 01/31/2012 | US8107314 Semiconductor storage device and method for producing semiconductor storage device |
| 01/31/2012 | US8107312 Memory chip array |
| 01/31/2012 | US8107311 Software programmable multiple function integrated circuit module |
| 01/31/2012 | US8107308 Semiconductor memory device |
| 01/31/2012 | US8107280 Word line voltage control in STT-MRAM |
| 01/31/2012 | US8107278 Semiconductor storage device |
| 01/31/2012 | US8106678 Semiconductor integrated circuits with power reduction mechanism |
| 01/26/2012 | US20120020179 Method and apparatus for word line decoder layout |
| 01/26/2012 | US20120020178 Multi-column addressing mode memory system including an integrated circuit memory device |
| 01/26/2012 | US20120020174 Asynchronous semiconductor memory capable of preventing coupling noise |
| 01/26/2012 | US20120020172 Data strobe signal generating device and a semiconductor memory apparatus using the same |
| 01/26/2012 | US20120020171 Memory system with delay locked loop (dll) bypass control |
| 01/26/2012 | US20120020145 Identification Circuit and Method for Generating an Identification Bit |
| 01/25/2012 | EP2410530A1 Memory chips and memory devices using the same |
| 01/25/2012 | EP2008281B1 Multi-port memory device having variable port speeds |
| 01/25/2012 | EP1805803B1 Scrambling method to reduce wordline coupling noise |
| 01/25/2012 | CN1725374B Semiconductor memory device including circuit to store access data |
| 01/25/2012 | CN101350220B Charge recycling operation method and driving circuit and low power memory thereof |
| 01/24/2012 | US8103848 Memory control device and information processing apparatus |
| 01/24/2012 | US8102730 Single-clock, strobeless signaling system |
| 01/24/2012 | US8102729 Resistive memory device capable of compensating for variations of bit line resistances |
| 01/24/2012 | US8102728 Cache optimizations using multiple threshold voltage transistors |
| 01/24/2012 | US8102727 Semiconductor memory device |
| 01/24/2012 | US8102710 System and method for setting access and modification for synchronous serial interface NAND |
| 01/24/2012 | US8102690 Bank re-assignment in chip to reduce IR drop |
| 01/19/2012 | WO2012009103A2 Method and apparatus for training a memory signal via an error signal of a memory |
| 01/19/2012 | WO2011140033A3 Techniques for refreshing a semiconductor memory device |
| 01/19/2012 | US20120014205 Semiconductor memory device for guaranteeing reliability of data transmission and semiconductor system including the same |
| 01/19/2012 | US20120014204 Semiconductor memory device for guaranteeing reliablity of data transmission and semiconductor system including the same |
| 01/19/2012 | US20120014203 Semiconductor memory apparatus |
| 01/19/2012 | US20120014202 Memory device and method |
| 01/19/2012 | US20120014197 Semiconductor device and test method thereof |
| 01/17/2012 | US8099620 Domain crossing circuit of a semiconductor memory apparatus |
| 01/17/2012 | US8098541 Non-volatile memory with stray magnetic field compensation |
| 01/17/2012 | US8098539 Hybrid single and dual channel DDR interface scheme by interleaving address/control signals during dual channel operation |
| 01/17/2012 | US8098535 Method and apparatus for gate training in memory interfaces |
| 01/17/2012 | US8098531 Semiconductor memory device |
| 01/12/2012 | US20120008452 Semiconductor integrated circuit capable of controlling read command |
| 01/12/2012 | US20120008451 Semiconductor memory device |
| 01/12/2012 | US20120008450 Flexible memory architecture for static power reduction and method of implementing the same in an integrated circuit |
| 01/12/2012 | US20120008437 Counter circuit, latency counter, semiconductor memory device including the same, and data processing system |
| 01/12/2012 | US20120008426 High speed dram architecture with uniform access latency |
| 01/12/2012 | US20120008378 Memory devices and methods having multiple address accesses in same cycle |
| 01/11/2012 | EP2405438A1 Method for writing in a MRAM-based memory device with reduced power consumption |
| 01/11/2012 | EP2404299A1 Nand flash architecture with multi-level row decoding |
| 01/11/2012 | CN1945741B Semiconductor memory device and transmission/reception system provided with the same |
| 01/11/2012 | CN1941174B Multi-port memory device |
| 01/11/2012 | CN1540666B Storage system with dynamic configurable and addressable content |
| 01/10/2012 | US8094510 Memory array incorporating noise detection line |
| 01/10/2012 | US8094509 Apparatus and method for placement of boosting cell with adaptive booster scheme |
| 01/10/2012 | US8094505 Method and system to lower the minimum operating voltage of a memory array |
| 01/10/2012 | US8094489 Semiconductor device |
| 01/05/2012 | US20120002500 Multi-Voltage Level, Multi-Dynamic Circuit Structure Device |
| 01/05/2012 | US20120002487 Nonvolatile memory apparatus and method for processing configuration information thereof |
| 01/05/2012 | US20120002486 Nonvolatile memory apparatus and method for processing configuration information thereof |
| 01/05/2012 | US20120002457 Semiconductor memory device and control method of the same |
| 01/04/2012 | EP1961009B1 Crossbar-array designs and wire addressing methods that tolerate misalignment of electrical components at wire overlap points |
| 01/03/2012 | US8089824 Memory controller with staggered request signal output |
| 01/03/2012 | US8089823 Processor instruction cache with dual-read modes |
| 01/03/2012 | US8089817 Precise tRCD measurement in a semiconductor memory device |
| 12/29/2011 | WO2011163022A2 Memory write operation methods and circuits |
| 12/29/2011 | WO2011106262A3 Hierarchical memory architecture |
| 12/29/2011 | US20110317509 Memory device word line drivers and methods |
| 12/29/2011 | US20110317508 Memory write operation methods and circuits |
| 12/29/2011 | US20110317507 Semiconductor memory and method for operating the semiconductor memory |
| 12/29/2011 | US20110317503 Semiconductor device |
| 12/29/2011 | US20110317502 Control of inputs to a memory device |
| 12/29/2011 | US20110317499 Split voltage level restore and evaluate clock signals for memory address decoding |
| 12/29/2011 | US20110317477 Cell structure for dual-port sram |
| 12/29/2011 | US20110317473 System and method for mitigating reverse bias leakage |
| 12/28/2011 | EP2399258A1 Multimode accessible storage facility |
| 12/28/2011 | CN1728278B 半导体装置的操作方法以及该半导体装置 Operating method of a semiconductor device and semiconductor device |
| 12/27/2011 | US8085616 Block decoder of a flash memory device |
| 12/27/2011 | US8085615 Multi-state resistance changing memory with a word line driver for applying a same program voltage to the word line |
| 12/27/2011 | US8085598 Nonvolatile semiconductor memory device |
| 12/27/2011 | US8085574 Nonvolatile ferroelectric memory and control device using the same |
| 12/22/2011 | US20110314213 Processor system using synchronous dynamic memory |
| 12/22/2011 | US20110310692 Sequential-write, random-read memory |
| 12/22/2011 | US20110310691 Multi-Port Memory Using Single-Port Memory Cells |
| 12/22/2011 | US20110310680 Interleave Memory Array Arrangement |
| 12/21/2011 | CN101453302B 解交织器、数据传输系统中的数据交织/解交织实现方法 Deinterleaver, the data transmission system of interleaving / deinterleaving Implementation |
| 12/21/2011 | CN101083131B 寄存器堆元件和电路以及操作寄存器堆电路的方法 Method and circuit element register file and operating the register file circuit |
| 12/21/2011 | CN101034587B 半导体存储装置中的地址缓冲器及缓冲地址的方法 The method of a semiconductor memory device in the address buffer and the buffer address |
| 12/20/2011 | US8081538 Semiconductor memory device and driving method thereof |
| 12/20/2011 | US8081537 Circuit for providing chip-select signals to a plurality of ranks of a DDR memory module |