| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 08/29/2013 | US20130223179 Delay locked loop circuit and semiconductor memory device including the same |
| 08/29/2013 | US20130223178 Global reset with replica for pulse latch pre-decoders |
| 08/29/2013 | US20130223177 Command decoders |
| 08/29/2013 | US20130223176 Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods |
| 08/29/2013 | US20130223167 Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system |
| 08/29/2013 | US20130223165 Memory devices and methods for high random transaction rate |
| 08/29/2013 | DE112010005970T5 Ablesen eines Speicherlements unter Zuhilfenahme eines Ringoszillators Reading a Speicherlements with the aid of a ring oscillator |
| 08/28/2013 | EP2630642A1 Memories and methods for performing atomic memory operations in accordance with configuration information |
| 08/27/2013 | US8520466 Internal command generation circuit |
| 08/27/2013 | US8520465 Semiconductor device |
| 08/27/2013 | US8520464 Interface circuit and semiconductor device incorporating same |
| 08/22/2013 | WO2013122884A1 Power-on-reset (por) circuits for resetting memory devices, and related circuits, systems, and methods |
| 08/22/2013 | US20130215702 Semiconductor memory apparatus, block decoder therefor, and decoding method thereof |
| 08/22/2013 | US20130215692 Semiconductor memory, memory system, and method of controlling the same |
| 08/21/2013 | EP2629300A2 Partial block erase architecture for flash memory |
| 08/21/2013 | CN203150141U Storage structure comprising multiple storage modules |
| 08/21/2013 | CN103258568A Memory device, memory controller and memory system |
| 08/21/2013 | CN103258566A Shift chain adopted integrated circuit |
| 08/21/2013 | CN101331457B 同步一位接口协议或数据结构 A synchronous interface protocol or data structures |
| 08/20/2013 | US8514654 Storage apparatus, substrate, liquid container, system, and control method of the storage apparatus |
| 08/20/2013 | US8514653 Multi-layered memory devices |
| 08/20/2013 | US8514652 Multiple-port memory device comprising single-port memory device with supporting control circuitry |
| 08/20/2013 | US8514651 Sharing access to a memory among clients |
| 08/20/2013 | US8514650 Semiconductor memory device |
| 08/15/2013 | US20130208556 Power-On-Reset (POR) Circuits for Resetting Memory Devices, and Related Circuits, Systems, and Methods |
| 08/15/2013 | US20130208553 Method for robust preamble location in a dqs signal |
| 08/15/2013 | US20130208546 Latency control circuit and semiconductor memory device comprising same |
| 08/13/2013 | US8509026 Word line boost circuit |
| 08/13/2013 | US8509025 Memory array circuit incorporating multiple array block selection and related method |
| 08/13/2013 | US8509020 Data processing system |
| 08/13/2013 | CA2415218C Method and apparatus for synchronization of row and column access operations |
| 08/08/2013 | US20130205100 Multi-port memory based on dram core |
| 08/08/2013 | US20130201779 Electronic apparatus, dram controller, and dram |
| 08/08/2013 | US20130201778 Semiconductor device capable of adjusting memory page size based on a row address and a bank address |
| 08/08/2013 | US20130201767 Semiconductor memory apparatus, operating method thereof, and data processing system using the same |
| 08/08/2013 | US20130201751 Multi-port memory based on dram core |
| 08/06/2013 | US8503260 Semiconductor memory device, method of testing the same and system of testing the same |
| 08/06/2013 | US8503250 High speed DRAM architecture with uniform access latency |
| 08/06/2013 | US8503211 Configurable module and memory subsystem |
| 08/01/2013 | US20130194884 Synchronous Global Controller For Enhanced Pipelining |
| 08/01/2013 | US20130194878 Semiconductor device including semiconductor memory circuit |
| 07/31/2013 | CN102044288B Method for converting electrical address and topological address of memory |
| 07/30/2013 | US8499030 Software and method that enables selection of one of a plurality of network communications service providers |
| 07/30/2013 | US8498175 Burst order control circuit |
| 07/30/2013 | US8498174 Dual-port subthreshold SRAM cell |
| 07/25/2013 | WO2013109680A1 Mimicking multi-voltage domain wordline decoding logic for a memory array |
| 07/24/2013 | EP2618267A1 Deterministic high integrity multi-processor system on a chip |
| 07/24/2013 | CN203085182U Asynchronous static random access memory based on IP (Internet Protocol) of synchronous static random access memory |
| 07/24/2013 | CN103222003A Memories and methods for performing atomic memory operations in accordance with configuration information |
| 07/23/2013 | US8493814 Semiconductor memory device using only single-channel transistor to apply voltage to selected word line |
| 07/23/2013 | US8493813 Row decoder circuit |
| 07/23/2013 | US8493812 Boost circuit for generating an adjustable boost voltage |
| 07/23/2013 | US8493811 Memory having asynchronous read with fast read output |
| 07/23/2013 | US8493809 Refresh control circuit and semiconductor memory apparatus using the same |
| 07/23/2013 | US8493486 Image pickup apparatus, image pickup system, and driving method of image pickup apparatus |
| 07/18/2013 | US20130182524 Semiconductor memory devices having internal clock signals and memory systems including such memory devices |
| 07/18/2013 | US20130182516 Semiconductor device having counter circuit |
| 07/18/2013 | US20130182514 Mimicking Multi-Voltage Domain Wordline Decoding Logic for a Memory Array |
| 07/18/2013 | DE102007039462B4 Verfahren und Vorrichtung zur Aufzählung Method and apparatus for enumeration |
| 07/16/2013 | US8488408 Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocks |
| 07/16/2013 | US8488407 Nonvolatile memory apparatus and method for processing configuration information thereof |
| 07/16/2013 | US8488400 Multi-port memory device |
| 07/11/2013 | WO2013102255A1 Device selection schemes in multi chip package nand flash memory system |
| 07/11/2013 | US20130176809 Self clocking for data extraction |
| 07/11/2013 | US20130176808 Word line boost circuit |
| 07/11/2013 | US20130176800 Memory controller having a write-timing calibration mode |
| 07/11/2013 | US20130176799 Semiconductor device, semiconductor system having the same, and command address setup/hold time control method therefor |
| 07/11/2013 | US20130176787 Method and Apparatus for Training a DLL in a Memory Subsystem |
| 07/10/2013 | CN103201795A Storage element reading using ring oscillator |
| 07/10/2013 | CN103198857A Programming method of memory array |
| 07/10/2013 | CN101611453B Independent link and bank selection |
| 07/09/2013 | US8484437 Data processing apparatus using pre-fetched data |
| 07/09/2013 | US8484436 Processor independent loop entry cache |
| 07/09/2013 | US8483006 Programmable addressing circuitry for increasing memory yield |
| 07/09/2013 | US8483005 Internal signal generator for use in semiconductor memory device |
| 07/09/2013 | US8483004 Semiconductor device with transistor storing data by change in level of threshold voltage |
| 07/09/2013 | US8483000 Semiconductor device |
| 07/09/2013 | US8482992 Method of controlling operations of a delay locked loop of a dynamic random access memory |
| 07/09/2013 | US8482991 Semiconductor device |
| 07/09/2013 | US8482954 Semiconductor memory and method for operating the semiconductor memory |
| 07/04/2013 | WO2013101459A1 Sharing local control lines across multiple planes in a memory device |
| 07/04/2013 | WO2013100956A1 Memory timing optimization using pattern based signaling modulation |
| 07/04/2013 | US20130170313 Wordline driver |
| 07/04/2013 | US20130170274 Semiconductor memory device storing memory characteristic information, memory module and memory system having the same, and operating method thereof |
| 07/02/2013 | US8477559 Burst termination control circuit and semiconductor memory using the same |
| 07/02/2013 | US8477558 Memory apparatuses with low supply voltages |
| 07/02/2013 | US8477557 Input circuit of semiconductor memory apparatus and controlling method thereof |
| 07/02/2013 | US8477556 Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlines |
| 07/02/2013 | US8477555 Deselect drivers for a memory array |
| 07/02/2013 | US8477545 Semiconductor apparatus |
| 07/02/2013 | US8477542 Semiconductor memory device |
| 07/02/2013 | US8477524 Nonvolatile memory devices and related methods and systems |
| 07/02/2013 | US8477521 Fuse circuit and memory device including the same |
| 07/02/2013 | US8476932 Multiplex gate driving circuit |
| 06/27/2013 | US20130166990 Memory circuit incorporating radiation-hardened memory scrub engine |
| 06/27/2013 | US20130163367 Clock generation circuit and semiconductor memory device employing the same |
| 06/27/2013 | US20130163366 Semiconductor memory device and operation method thereof |
| 06/27/2013 | US20130163365 Semiconductor device having high-voltage transistor |
| 06/27/2013 | US20130163364 Semiconductor memory device and method for driving the same |
| 06/26/2013 | EP2608207A1 Semiconductor device with through-silicon vias |